Note:
There are two bits in the flags register which are documented by Zilog as being unused. But in fact these bits do change: these bits are updated according to an undocumented register of the Z80 named either WZ or MEMPTR. This undocumented register is used to store temporary results such as 16-bits arithmetic results, and address (for example, loading I register and the vector byte for interruption mode 2 to compute the value to load in PC register).
== Sign flag ==
* If the LDIR/LDDR opcode is overwritten by itself then command execution will stop. Effectively, the LDIR opcode is repeatidly fetched and decoded for each byte fetched from memory.
== IFF0 and IFF1 and IFF2 ==IFF0 IFF1 reflects the state of the maskable interrupt. The maskable interrupt can be enabled using the Z80 instruction "EI" and disabled using the Z80 instruction "DI". When IFF0 IFF1 is "1" masked interrupts are enabled, when a interrupt request is received by the Z80 it will be acknowledged and the interrupt handler executed. When IFF0 IFF1 is "0" masked interrupts are disabled, any interrupt requests are ignored.
When a non-maskable interrupt (NMI) is executed by the Z80, IFF1 IFF2 is set to the value of IFF0IFF1. Then IFF0 IFF1 is set to "0" to disable maskable interrupts. The NMI handler will be executed.When a "RETN" instruction is executed by the Z80, IFF0 IFF1 is set to the value in IFF1IFF2, therefore the maskable interrupt state is restored. The state of IFF0 IFF1 can be set at any time using the "DI" and "EI" instructions.
== IM 0, IM 1, IM 2 ==
* The instructions "IM 0 ","IM 1" and "IM 2" set the Z80 interrupt mode which defines the actions taken to execute the maskable interrupt handler.
[[Category:Programming]]