Difference between revisions of "V9990"
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* In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF. | * In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF. | ||
| − | + | * When reading 2bpp data with the POINT command the data appears to have undergone a circular shift so that the pixel you are interested in has it's value in the top 2 bits. | |
| + | e.g. | ||
| + | X = 0 | ||
| + | aabbccdd | ||
| + | x = 1 | ||
| + | bbccddaa | ||
| + | x = 2 | ||
| + | ccddaabb | ||
| + | x = 3 | ||
| + | ddaabbcc | ||
| + | |||
[[Category:Hardware]] | [[Category:Hardware]] | ||
Revision as of 10:35, 14 October 2018
The V9990 E-VDP-III or 'Graphics 9000' is a Video Display Processor (VDP) by Yamaha which is based on an unreleased VDP (V9978) that was intended for the unreleased MSX3.
This chip is available on graphics cards for the MSX and CPC.
Documentation
Programming Documentation Manual for the V9990 VDP from Yamaha as a PDF.
Technical
The official 'Application Manual' describes the V9990 ports, registers and commands. These additional notes apply to the V9990 used in the CPC Powergraph video board and explain details that are not clearly described or are omitted from the manual.
- In the following "databus" means that the v9990 doesn't assert the bus, it doesn't provide data, so the value read is "floating-bus" or the value on the z80 databus at the time. More commonly on CPC it's &ff, but there are some configurations of CPC where this differs.
- Reading from the Kanji ROM ports without a Kanji ROM returns databus values
- Reading from the write only ports (or unused ports) returns databus values.
- Palette red data has a mask of &9F (bits red and color key bit), blue and green have a mask of 0x01f.
e.g.
LD BC,&FF64 LD A,14 OUT (C),C LD BC,&FF63 LD A,0 OUT (C),A LD BC,&FF61 LD A,&FF ;; <- reading this component back returns &9F OUT (C),A LD A,&FF ;; <- reading this component back returns &1F OUT (C),A LD A,&FF ;; <- reading this component back returns &1F OUT (C),A
- Bits 1,0 of R14 define a ternary counter. If counter is set to 3 then reads will return 0 and writes are ignored. If auto increment is enabled, it will increment as normal. When ternary counter is 2 or 3, then palette index will increment and ternary counter will go to 0.
e.g.
LD BC,&FF64 LD A,14 OUT (C),C LD BC,&FF63 LD A,3 OUT (C),A LD BC,&FF61 LD A,&FF OUT (C),A ;; write is not done.
LD BC,&FF64 LD A,14 OUT (C),C LD BC,&FF63 LD A,3 OUT (C),A LD BC,&FF61 IN A,(C) ;; read returns last value written to port
e.g.
LD BC,&FF64 LD A,14 OUT (C),C LD BC,&FF63 LD A,2 OUT (C),A LD BC,&FF61 LD A,&FF OUT (C),A ;; palette index will be 1, and ternary counter is 0.
- If a command transfers data, and it requests data to be written to the command data port, then you can't use a read of this port to clear the data request. It must be a write. Similarly, if a command requests data to be read then you can use a write to clear the data request.
- If you read from a write-only register you will see data-bus value because the V9990 doesn't assert data on the bus.
- After reset (including software reset using the control port), all registers are reset to 0. In addition the selected register (port 4) is set to 0 and read and write increment are not inhibited.
- If using software reset and the reset is held, then reading from ports will cause the CPC to hang. I believe it's asserting /WAIT, but I can't confirm.
- Some registers have additional bits which are not documented. The mask describes which bits are read/write and which are unchanged.
Where the mask has a '1' bit, this bit is read/write. Where the mask has a '0' bit this bit remains at 0 and can't be changed.
- Register 7 (SCREEN MODE): Mask is &FF. - Register 9 (INTERRUPT READ/WRITE): Mask is &87 - Register 15 (BACK DROP COLOR): Mask is &FF - Register 22 (SCROLL CONTROL): Mask is &C1 - Register 25 (SPRITE PATTERN GENERATOR TABLE BASE ADDRESS): Mask is &CF - Register 26 (LCD CONTROL): Mask is &FF - Register 27 (PRIORITY CONTROL): Mask is &FF
- VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield different data because the addresses are translated from physical to logical based on the mode.
- In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (ever even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF.
- When reading 2bpp data with the POINT command the data appears to have undergone a circular shift so that the pixel you are interested in has it's value in the top 2 bits.
e.g.
X = 0 aabbccdd x = 1 bbccddaa x = 2 ccddaabb x = 3 ddaabbcc
