The IBM System 34 double density format is a structure used by NEC765 compatible disc controllers when reading and writing in MFM mode.
The data has this form:
Gap 0 (80 bytes of data 4E)
Sync Pre-amble (12 bytes of 0)
Index mark IDAM which contains 3 bytes of C2 (which have a missing clock) followed by 1 byte FC.
Gap 1 (50 bytes of data 4e)
Then follows the data for each sector:
Sync Pre-amble (12 bytes of 0)
ID mark IDAM which contains 3 bytes of A1 (which have a missing clock) followed by 1 byte FE.
1 byte 'C' (defined by FDC format command)
Gap 2 (22 bytes of 4E)
The CRC for the ID field is computed from the 3 bytes of A1, the 1 byte FE, ID mark and C,H,R and N. When verifying include the CRC bytes and if the result is 0, then the CRC is correct.
Then comes the data field for the sector:
Sync Pre-amble (12 bytes of 0)
Data mark IDAM which contains 3 bytes of A1 (which have a missing clock) followed by 1 byte FB for Data or F8 for Deleted Data.
'n' bytes of sector data (defined by format when formatting, or by ID field when reading/writing)
2 bytes CRC (stored big endian)
Gap 3 ('n' bytes of data 4E) (defined by FDC format command)
The CRC for the data field is computed from the 3 bytes of A1, the Data mark and the data bytes. When verifying include the CRC bytes and if the result is 0 then the CRC is correct.
After the last sector:
Gap 4 ('n' bytes of 4E all the way to the end of the track).
NOTE: * The initial layout is defined by the format command.* When writing the FDC will replace the data field entirely with the data written creating splice points in gap2 and gap3 areas.* A1/C2 are the only MFM-words which have a missing clock. All the others are written like normal data bytes. ===CRC=== The CRC is initialised to FFFF. It is updated byte by byte and uses the CCITT-CRC16 algorithm. It is written after the ID and data field high byte and then low byte. ===Data separator syncing=== The pre-amble is 12 bytes of 0 which are used to prime and synchronize the data separator with the data bits and clock bits.0 encodes as AAAA and has clock bits of '1' and data bits of '0' interleaved. The data separator expects a continuous stream of 0 bits to sync and maintains a count of them. If the separator sees a 1 data bit during this time then it will re-sync and reset it's internal count to 0. When a certain count is reached then the data separator is synced and it will output separate clocks and data to the FDC. Amstrad uses these data separators:* SED9420C* FDC9216 These differ in the number of bits required for sync.
===SyncingFDC syncing and Address Mark ===
In order to read The address mark sync is for the data correctly FDC and to ensure marks where the bits are in the expected order data structure starts. The FDC expects this within a specific bit pattern is used for syncing. This bit pattern is specific to certain time after the format used by the FDCdata separator has synced.
When this special pattern is recognised recognized then all data following is synced and will always read the same.
This special value used by the NEC765 is 4489 and has the following properties.
* 4489 is an encoded version of the data byte A1 and has bit 7 set. It doesn't matter what the value of the previous byte is, the first clock of 4489 will always be 0. Therefore the pattern 4489 can't be influenced by data around it.
* To make the value special, it has a "missing clock". What this means is that one of cell which encodes the clocks is forced to 0clock and data bit has no clock. The equivalent A1 byte encoded to MFM without the missing clock is different, therefore it is unique.