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/* CSYNC signal */
Also designated as Video gate Array (VGA, not to be confused with IBM PC compatible graphic card spec).
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== Introduction ==
The gate array Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.
In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
In the [[KC Compact]] system, the functions of the Gate-Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a ASIC.
The Gate Array is described here is the one found in a standard CPC.
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== What does it do? ==
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.
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== Interrupt management ==
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
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== CSYNC signal ==
On CPC, the HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified and merged by the Gate Array as C-HSYNC and C-VSYNC and then merged into a single CSYNC signal that will be sent to the display.
When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.
C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.
On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array.The electron beam is basically turned off. Turning up the brightness level won't make it any brighter. <br>
== Controlling the Gate Array ==
This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function is performed in a memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.
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== Register 0 - Palette Index (Pen selection) ==
| 0 || x
|}
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== Register 1 - Palette Data (Colour selection) ==
| 0 || x
|}
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== Register 2 - Select screen mode and ROM configuration ==
| 0 || x
|}
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== Register 3 - RAM Banking ==
The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.
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== Programming the Gate Array - Examples ==
ret
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== Video memory structure ==
{|{{Prettytable|width: 700px; font-size: 2em;}}
|rowspan=2|'''Graphics Mode'''||colspan=8 style="text-align: center;"|'''VRAM byte'''||colspan=8 style="text-align: center;"|'''Displayed Pixels'''||rowspan=2|'''Definition'''
|-
|'''7'''
|2 pixels in 4 colors
|}
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== Split rasters ==
To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.
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== Palette R,G,B definitions ==
They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.
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== Pictures ==
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>
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==See also==
*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
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== External links ==
