Changes
/* CSYNC */
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
== CSYNC ==
On CPC, the HSYNC and VSYNC signals are received from the CRTC. These signals are then converted and merged by the Gate Array into a single CSYNC signal that will be sent to the display.
The Gate Array uses 2 internal counters to create its CSYNC signal:
* H06 which counts the number of CRTC characters processed during an HSYNC
* V26 which counts the number of HSYNCs occuring during a VSYNC
== Controlling the Gate Array ==
== Register 3 - RAM Banking ==
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PALchip]] that assists the Gate Array chip.
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