Changes
/* Introduction */
== Introduction ==
The gate array Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.
In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
In the [[KC Compact]] system, the functions of the Gate-Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a ASIC.
The Gate Array is described here is the one found in a standard CPC.
