Changes
CRTC
,/* DISPTMG */
1. The function of these I/O ports is dependant on the CRTC type
2. If The CRTC is not connected to the CPU's RD and WR pins, so the CRTC is not aware of the CPU bus I/O direction. Therefore, if you perform an IN instruction to the select or write functions , it will write data to the CRTC from the current data on the bus.
==Addressing==
== DISPTMG ==
DISPTMG signal defines the border. When DISPTMG is "1" the border colour is output by the Gate-Array to the display. The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.
The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
The DISPTMG can be forced using R8 (DISPTMG Skew) on type 0,3 and 4 or by setting R6=0 on type 1. It is not possible to force the DISPTMG on type 2.
== HSYNC and VSYNC ==
'''Notes'''
* On types 0 and 1, if a Write Only register is read from, "0" is returned.
Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.
In demos to make a display compatible with all CRTCs , program R12/R13 when VCC!=0. This will then take effect at the next frame start.
=== UM6845R status register ===
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [https://pulkomandy.github.io/shinra.github.io/crtc.html Differences between CRTC types]
* [[Media:Dossier Rupture(Gozeur Paradox).pdf]]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
