Changes
ASIC
,/* New features */
This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".
*12-bit colour palette*Hardware Sprites.sprites*Soft Vertical and horizontal per-pixel hardware soft scrolling (in complement with register 12&13 of the CRTC)
*Screen splitting
*Programmable and vectorised raster interrupts*Vectored interrupts
*DMA sound channels
*Specific ROM switching
*8-bit printer port (with bit3 of CRTC register 12)
*Analog joystick port
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== Programmable Raster Interrupt ==
The 8-bit memory-mapped register PRI (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic R52 raster interrupt system of the [[Gate Array]] R52 raster interrupt system instead.
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* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
* Bits2..0 are the channel enable bits. When set to "1" it enables the corresponding DMA channel. It can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.
* Bits7..4 are the interrupt bits. An interrupt bit is set to "0" when the corresponding channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is active at "0" if at least one of the interrupt bits is "0".
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== Vectored Interrupt ==
The ASIC provides an interrupt vector on interrupt request.
The register IVR (at address 6805h) supplies the top 5 bits of the vector provided to the CPU. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt mode, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the IVR register are unused.
Bit0 of the IVR register controls whether DMA channel interrupts are automatically cleared.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
==== Interrupt Vector used on Z80 IM2 mode ====
{| class="wikitable"
|-
!Interrupt Vector
!Signal source
!Value
|-
|A15..A8||Z80||Register I
|-
|A7..A3||ASIC||IVR register bits7..3
|-
|A2..A1||ASIC||00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA raster
|-
|A0||ASIC||Always 0
|}
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