* The channel enable bits in this register enable each "DMA" channel separately, and can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.
* The interrupt bits are set when a channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is "0" if at least one of the interrupt bits is "0".
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