*Specific ROM switching
*8-bit printer port (with bit3 of CRTC register 12)
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== Split Screen ==
The 8-bit register SPLT (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value after power-on reset) will disable the split screen feature.
The 16-bit register SSA (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. These registers work similarly to R12/R13 in the CRTC. This configuration allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screen.
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An 8-bit memory-mapped register (PRI) has been added within the ASIC at address 6800h, which is cleared at power up:
*When PRI=0, the classic R52 raster interrupt system of the [[Gate Array]] functions as before*Otherwise, we have a programmable raster interrupt system instead: an interrupt will occur at the end of the scan line specified in PRI
The PRI can be reprogrammed as required to produce multiple interrupts per frame.