* While the syntax of ADD, ADC and SBC instructions all explicitely mention the A register, the SUB instruction does not mention it.
* The 16-bit commands ADD HL,ss, ADC HL,ss and SBC HL,ss exist but not the command SUB HL,ss.
* When an LDxR / CPxR / INxR / OTxR instruction completes normally, the flags are exactly as described in the reference above. However, when they are interrupted, the interrupt handler sees some flags in a different state. [https://github.com/hoglet67/Z80Decoder/wiki/Undocumented-Flags#interrupted-block-instructions Source]
* The values of F5 and F3 following an SCF or CCF instruction depend on whether the preceding instruction modified the flags or not. [https://github.com/hoglet67/Z80Decoder/wiki/Undocumented-Flags Source]
* The BIT b,(HL) instruction exposes certain bits of the internal register WZ to the undocumented flags F5 and F3. [https://zx-pk.ru/attachment.php?attachmentid=2989 Source]