6502 info taken from Wikipedia.org
The MOS Technology 6502 is an 8-bit microprocessor designed by Chuck Peddle for MOS Technology in 1975. When it was introduced it was the least expensive full featured CPU on the market by far, at about 1/6th the price, or less, of competing designs from larger companies such as Motorola and Intel. It was nevertheless faster than most of them, and, along with the Zilog Z80, sparked off a series of computer projects that would eventually result in the home computer revolution of the 1980s. The 6502 design was originally second-sourced by Rockwell and Synertek and later licensed to a number of companies; it is still made for embedded systems.
The 6502 was used, among others, for Commodore's 8-bit machines.
Originally the CPC was destined to be designed around the 6502 processor. But when Amstrad approached Locomotive Software to develop a Basic for it with a very tight deadline, Locomotive PLC, who already had a Z80 Basic in the works, urged and convinced Amstrad to switch to the Z80.
Registers
| Register | Size | Description | Notes |
|---|---|---|---|
| A (Accumulator) | 8-bit | Main register for arithmetic, logic, and data transfer | Most operations use this register |
| X (Index Register X) | 8-bit | Used for indexing memory and loop counters | Can be used for addressing modes like Indexed Indirect, Zero Page Indexed, and Absolute Indexed |
| Y (Index Register Y) | 8-bit | Used for indexing memory and loop counters | Often used in Absolute and Zero Page Indexed addressing |
| P (Processor Status) | 8-bit |
|
The status register is modified by arithmetic and logic operations, as well as interrupts |
| S (Stack Pointer) | 8-bit | Points to the current location in the stack | Stack is located in page 1 ($0100-$01FF), 8-bit S is offset to this base |
| PC (Program Counter) | 16-bit | Points to the next instruction to be executed | Automatically increments as instructions are executed |
6502 Instruction set
For cycles, p=1 if page is crossed, t=1 if branch is taken.
Letter A
| Instruction | Opcode | Cycles | N | V | B | D | I | Z | C | Operation | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ADC #$nn | $69 | 2 | + | + | - | - | - | + | + | A + M + C → A, C | Add Memory to Accumulator with Carry |
| ADC $nnnn | $6D | 4 | |||||||||
| ADC $nnnn,X | $7D | 4+p | |||||||||
| ADC $nnnn,Y | $79 | 4+p | |||||||||
| ADC $nn | $65 | 3 | |||||||||
| ADC $nn,X | $75 | 4 | |||||||||
| ADC ($nn,X) | $61 | 6 | |||||||||
| ADC ($nn),Y | $71 | 5+p | |||||||||
| ANC #$nn | $0B | 2 | + | - | - | - | - | + | + | A ∧ M → A, N → C | "AND" Memory with Accumulator then Move Negative Flag to Carry Flag |
| ANC #$nn | $2B | 2 | |||||||||
| AND #$nn | $29 | 2 | + | + | - | - | - | + | - | A ∧ M → A | "AND" Memory with Accumulator |
| AND $nnnn | $2D | 4 | |||||||||
| AND $nnnn,X | $3D | 4+p | |||||||||
| AND $nnnn,Y | $39 | 4+p | |||||||||
| AND $nn | $25 | 3 | |||||||||
| AND $nn,X | $35 | 4 | |||||||||
| AND ($nn,X) | $21 | 6 | |||||||||
| AND ($nn),Y | $31 | 5+p | |||||||||
| ARR #$nn | $6B | 2 | + | + | - | - | - | + | + | (A ∧ M) / 2 → A | "AND" Accumulator then Rotate Right |
| ASL A | $0A | 2 | + | - | - | - | - | + | + | C ← /M7...M0/ ← 0 | Arithmetic Shift Left |
| ASL $nnnn | $0E | 6 | |||||||||
| ASL $nnnn,X | $1E | 7 | |||||||||
| ASL $nn | $06 | 5 | |||||||||
| ASL $nn,X | $16 | 6 | |||||||||
| ASR #$nn | $4B | 2 | 0 | - | - | - | - | + | + | (A ∧ M) / 2 → A | "AND" then Logical Shift Right |
Official opcode matrix
| Addressing modes: A - accumulator, # - immediate, zpg - zero page, abs - absolute, ind - indirect, X - indexed by X register, Y - indexed by Y register, rel - relative | ||||||||||||
| High nibble | Low nibble | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 4 | 5 | 6 | 8 | 9 | A | C | D | E | |
| 0 | BRK | ORA (ind,X) | ORA zpg | ASL zpg | PHP | ORA # | ASL A | ORA abs | ASL abs | |||
| 1 | BPL rel | ORA (ind),Y | ORA zpg,X | ASL zpg,X | CLC | ORA abs,Y | ORA abs,X | ASL abs,X | ||||
| 2 | JSR abs | AND (ind,X) | BIT zpg | AND zpg | ROL zpg | PLP | AND # | ROL A | BIT abs | AND abs | ROL abs | |
| 3 | BMI rel | AND (ind),Y | AND zpg,X | ROL zpg,X | SEC | AND abs,Y | AND abs,X | ROL abs,X | ||||
| 4 | RTI | EOR (ind,X) | EOR zpg | LSR zpg | PHA | EOR # | LSR A | JMP abs | EOR abs | LSR abs | ||
| 5 | BVC rel | EOR (ind),Y | EOR zpg,X | LSR zpg,X | CLI | EOR abs,Y | EOR abs,X | LSR abs,X | ||||
| 6 | RTS | ADC (ind,X) | ADC zpg | ROR zpg | PLA | ADC # | ROR A | JMP (ind) | ADC abs | ROR abs | ||
| 7 | BVS rel | ADC (ind),Y | ADC zpg,X | ROR zpg,X | SEI | ADC abs,Y | ADC abs,X | ROR abs,X | ||||
| 8 | STA (ind,X) | STY zpg | STA zpg | STX zpg | DEY | TXA | STY abs | STA abs | STX abs | |||
| 9 | BCC rel | STA (ind),Y | STY zpg,X | STA zpg,X | STX zpg,Y | TYA | STA abs,Y | TXS | STA abs,X | |||
| A | LDY # | LDA (ind,X) | LDX # | LDY zpg | LDA zpg | LDX zpg | TAY | LDA # | TAX | LDY abs | LDA abs | LDX abs |
| B | BCS rel | LDA (ind),Y | LDY zpg,X | LDA zpg,X | LDX zpg,Y | CLV | LDA abs,Y | TSX | LDY abs,X | LDA abs,X | LDX abs,Y | |
| C | CPY # | CMP (ind,X) | CPY zpg | CMP zpg | DEC zpg | INY | CMP # | DEX | CPY abs | CMP abs | DEC abs | |
| D | BNE rel | CMP (ind),Y | CMP zpg,X | DEC zpg,X | CLD | CMP abs,Y | CMP abs,X | DEC abs,X | ||||
| E | CPX # | SBC (ind,X) | CPX zpg | SBC zpg | INC zpg | INX | SBC # | NOP | CPX abs | SBC abs | INC abs | |
| F | BEQ rel | SBC (ind),Y | SBC zpg,X | INC zpg,X | SED | SBC abs,Y | SBC abs,X | INC abs,X | ||||
| Blank opcodes (e.g., F2) and all opcodes whose low nibbles are 3, 7, B and F are undefined in the official 6502 instruction set. | ||||||||||||
Opcode matrix including illegal opcodes
| High nibble | Low nibble | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | |
| 0 | BRK | ORA (ind,X) | JAM | SLO (ind,X) | NOP zpg | ORA zpg | ASL zpg | SLO zpg | PHP | ORA # | ASL A | ANC # | NOP abs | ORA abs | ASL abs | SLO abs |
| 1 | BPL rel | ORA (ind),Y | JAM | SLO (ind),Y | NOP zpg,X | ORA zpg,X | ASL zpg,X | SLO zpg,X | CLC | ORA abs,Y | NOP | SLO abs,Y | NOP abs,X | ORA abs,X | ASL abs,X | SLO abs,X |
| 2 | JSR abs | AND (ind,X) | JAM | RLA (ind,X) | BIT zpg | AND zpg | ROL zpg | RLA zpg | PLP | AND # | ROL A | ANC # | BIT abs | AND abs | ROL abs | RLA abs |
| 3 | BMI rel | AND (ind),Y | JAM | RLA (ind),Y | NOP zpg,X | AND zpg,X | ROL zpg,X | RLA zpg,X | SEC | AND abs,Y | NOP | RLA abs,Y | NOP abs,X | AND abs,X | ROL abs,X | RLA abs,X |
| 4 | RTI | EOR (ind,X) | JAM | SRE (ind,X) | NOP zpg | EOR zpg | LSR zpg | SRE zpg | PHA | EOR # | LSR A | ALR # | JMP abs | EOR abs | LSR abs | SRE abs |
| 5 | BVC rel | EOR (ind),Y | JAM | SRE (ind),Y | NOP zpg,X | EOR zpg,X | LSR zpg,X | SRE zpg,X | CLI | EOR abs,Y | NOP | SRE abs,Y | NOP abs,X | EOR abs,X | LSR abs,X | SRE abs,X |
| 6 | RTS | ADC (ind,X) | JAM | RRA (ind,X) | NOP zpg | ADC zpg | ROR zpg | RRA zpg | PLA | ADC # | ROR A | ARR # | JMP (ind) | ADC abs | ROR abs | RRA abs |
| 7 | BVS rel | ADC (ind),Y | JAM | RRA (ind),Y | NOP zpg,X | ADC zpg,X | ROR zpg,X | RRA zpg,X | SEI | ADC abs,Y | NOP | RRA abs,Y | NOP abs,X | ADC abs,X | ROR abs,X | RRA abs,X |
| 8 | NOP # | STA (ind,X) | NOP # | SAX (ind,X) | STY zpg | STA zpg | STX zpg | SAX zpg | DEY | NOP # | TXA | ANE # | STY abs | STA abs | STX abs | SAX abs |
| 9 | BCC rel | STA (ind),Y | JAM | SHA (ind),Y | STY zpg,X | STA zpg,X | STX zpg,Y | SAX zpg,Y | TYA | STA abs,Y | TXS | TAS abs,Y | SHY abs,X | STA abs,X | SHX abs,Y | SHA abs,Y |
| A | LDY # | LDA (ind,X) | LDX # | LAX (ind,X) | LDY zpg | LDA zpg | LDX zpg | LAX zpg | TAY | LDA # | TAX | LXA # | LDY abs | LDA abs | LDX abs | LAX abs |
| B | BCS rel | LDA (ind),Y | JAM | LAX (ind),Y | LDY zpg,X | LDA zpg,X | LDX zpg,Y | LAX zpg,Y | CLV | LDA abs,Y | TSX | LAS abs,Y | LDY abs,X | LDA abs,X | LDX abs,Y | LAX abs,Y |
| C | CPY # | CMP (ind,X) | NOP # | DCP (ind,X) | CPY zpg | CMP zpg | DEC zpg | DCP zpg | INY | CMP # | DEX | AXS # | CPY abs | CMP abs | DEC abs | DCP abs |
| D | BNE rel | CMP (ind),Y | JAM | DCP (ind),Y | NOP zpg,X | CMP zpg,X | DEC zpg,X | DCP zpg,X | CLD | CMP abs,Y | NOP | DCP abs,Y | NOP abs,X | CMP abs,X | DEC abs,X | DCP abs,X |
| E | CPX # | SBC (ind,X) | NOP # | ISC (ind,X) | CPX zpg | SBC zpg | INC zpg | ISC zpg | INX | SBC # | NOP | SBC # | CPX abs | SBC abs | INC abs | ISC abs |
| F | BEQ rel | SBC (ind),Y | JAM | ISC (ind),Y | NOP zpg,X | SBC zpg,X | INC zpg,X | ISC zpg,X | SED | SBC abs,Y | NOP | ISC abs,Y | NOP abs,X | SBC abs,X | INC abs,X | ISC abs,X |
Block Diagram
