6502 info taken from Wikipedia.org
The MOS Technology 6502 is an 8-bit microprocessor designed by Chuck Peddle for MOS Technology in 1975. When it was introduced it was the least expensive full featured CPU on the market by far, at about 1/6th the price, or less, of competing designs from larger companies such as Motorola and Intel. It was nevertheless faster than most of them, and, along with the Zilog Z80, sparked off a series of computer projects that would eventually result in the home computer revolution of the 1980s. The 6502 design was originally second-sourced by Rockwell and Synertek and later licensed to a number of companies; it is still made for embedded systems.
The 6502 was used, among others, for Commodore's 8-bit machines.
Originally the CPC was destined to be designed around the 6502 processor. But when Amstrad approached Locomotive Software to develop a Basic for it with a very tight deadline, Locomotive PLC, who already had a Z80 Basic in the works, urged and convinced Amstrad to switch to the Z80.
Opcode matrix for the 6502 instruction set
| Addressing modes: A - accumulator, # - immediate, zpg - zero page, abs - absolute, ind - indirect, X - indexed by X register, Y - indexed by Y register, rel - relative | ||||||||||||
| High nibble | Low nibble | |||||||||||
| 0 | 1 | 2 | 4 | 5 | 6 | 8 | 9 | A | C | D | E | |
| 0 | BRK | ORA (ind,X) | ORA zpg | ASL zpg | PHP | ORA # | ASL A | ORA abs | ASL abs | |||
| 1 | BPL rel | ORA (ind),Y | ORA zpg,X | ASL zpg,X | CLC | ORA abs,Y | ORA abs,X | ASL abs,X | ||||
| 2 | JSR abs | AND (ind,X) | BIT zpg | AND zpg | ROL zpg | PLP | AND # | ROL A | BIT abs | AND abs | ROL abs | |
| 3 | BMI rel | AND (ind),Y | AND zpg,X | ROL zpg,X | SEC | AND abs,Y | AND abs,X | ROL abs,X | ||||
| 4 | RTI | EOR (ind,X) | EOR zpg | LSR zpg | PHA | EOR # | LSR A | JMP abs | EOR abs | LSR abs | ||
| 5 | BVC rel | EOR (ind),Y | EOR zpg,X | LSR zpg,X | CLI | EOR abs,Y | EOR abs,X | LSR abs,X | ||||
| 6 | RTS | ADC (ind,X) | ADC zpg | ROR zpg | PLA | ADC # | ROR A | JMP (ind) | ADC abs | ROR abs | ||
| 7 | BVS rel | ADC (ind),Y | ADC zpg,X | ROR zpg,X | SEI | ADC abs,Y | ADC abs,X | ROR abs,X | ||||
| 8 | STA (ind,X) | STY zpg | STA zpg | STX zpg | DEY | TXA | STY abs | STA abs | STX abs | |||
| 9 | BCC rel | STA (ind),Y | STY zpg,X | STA zpg,X | STX zpg,Y | TYA | STA abs,Y | TXS | STA abs,X | |||
| A | LDY # | LDA (ind,X) | LDX # | LDY zpg | LDA zpg | LDX zpg | TAY | LDA # | TAX | LDY abs | LDA abs | LDX abs |
| B | BCS rel | LDA (ind),Y | LDY zpg,X | LDA zpg,X | LDX zpg,Y | CLV | LDA abs,Y | TSX | LDY abs,X | LDA abs,X | LDX abs,Y | |
| C | CPY # | CMP (ind,X) | CPY zpg | CMP zpg | DEC zpg | INY | CMP # | DEX | CPY abs | CMP abs | DEC abs | |
| D | BNE rel | CMP (ind),Y | CMP zpg,X | DEC zpg,X | CLD | CMP abs,Y | CMP abs,X | DEC abs,X | ||||
| E | CPX # | SBC (ind,X) | CPX zpg | SBC zpg | INC zpg | INX | SBC # | NOP | CPX abs | SBC abs | INC abs | |
| F | BEQ rel | SBC (ind),Y | SBC zpg,X | INC zpg,X | SED | SBC abs,Y | SBC abs,X | INC abs,X | ||||
| Blank opcodes (e.g., F2) and all opcodes whose low nibbles are 3, 7, B and F are undefined in the 6502 instruction set. | ||||||||||||