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/* PAL MMR register */
== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the [[Gate Array ]] can only access the Base 64k page of RAM.
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== PAL I/O port ==
Note that no settings are stored in the Gate Array itself regarding register 3 (the MMR)register. But the PAL and Gate Array share an I/O port address so that it appears to be the same chip to the programmer.
Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, 4.
