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Z80

18 bytes added, 3 February
/* The Decode ROM (PLA) */
The Z80 is based around a more complicated structure than the 6502. Here the instruction is sent through a (rather) simple decoder. The decoder is built from a PLA. Simple because 8080/Z80 code offer fewer variants (i.e. addressing modes) and is quite regular compared with a 6502. The decoder creates multiple lines for each instruction or instruction group, which are fed into the second stage.
Two counters are set up in parallel. One counting the Memory (or Machine) states (M1..M5), the other Time states (T1..T5) within (*1note1). With a new instruction the M counter gets reset to 1, with each M state the T counter gets reset.
The second stage of instruction decode is something that is much like another PLA, but built out of single gates (*2note2). The gates are set up much like a grid with the timing signals (M1..M5 & T1..T5) as horizontal input and the PLA output (instructions/instruction groups) as vertical input. The gate is built along the vertical line and combining its signal with one or more timing signals using AND/NOR logic (*3note3). The output of these gates are fed into the discrete logic of the execution units. [https://retrocomputing.stackexchange.com/questions/6656/how-was-microcode-implemented-in-retro-processors Source]
*1 - note1: this internal structure is also the reason for this otherwise unusual notation used throughout all Z80 documentation.
*2 - note2: The structure is quite similar to a gate array - except that only needed inputs/functions are cast into silicon.
*3 - note3: CMOS offers the feature to build rather complex gates with multiple inputs in a simple way - to some extend this is maybe the most unique feature about the Z80 design.
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