== Block Diagram ==
[[File:Z80 Block Diagram.gif]]
== Manuals ==
*[[Media:Um0080.pdf|Official Zilog Z80 CPU user manual (2016)]]
*[[Media:Z80 CPU Technical Manual 1977.pdf]]
*[[Media:Mostek Z80 Programming Manual.pdf]]
== Weblinks ==
*[[Zilog]] [http://www.zilog.com]
*[http://www.z80.info/z80cs.htm Computer Systems based on Z80 Family]
*[http://en.wikipedia.org/wiki/Z80 The Z80 processor on Wikipedia]
*[https://www.grimware.org/doku.php/documentations/devices/z80 Z80 documentation from Grimware]
*[https://floooh.github.io/2021/12/06/z80-instruction-timing.html Detailed look at Z80 instruction timings with the help of a Z80 netlist simulation]
== Registers==
* Contrarily to what the syntax of the instructions JP (HL/IX/IY) suggest, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY
* While the syntax of ADD, ADC and SBC instructions all explicitely mention the A register, the SUB instruction does not mention it
<br>
== Manuals ==
*[[Media:Um0080.pdf|Official Zilog Z80 CPU user manual (2016)]]
*[[Media:Z80 CPU Technical Manual 1977.pdf]]
*[[Media:Mostek Z80 Programming Manual.pdf]]
<br>
== Weblinks ==
*[[Zilog]] [http://www.zilog.com]
*[http://www.z80.info/z80cs.htm Computer Systems based on Z80 Family]
*[http://en.wikipedia.org/wiki/Z80 The Z80 processor on Wikipedia]
*[https://www.grimware.org/doku.php/documentations/devices/z80 Z80 documentation from Grimware]
*[https://floooh.github.io/2021/12/06/z80-instruction-timing.html Detailed look at Z80 instruction timings with the help of a Z80 netlist simulation]
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:CPC Internal Components]][[Category:Electronic Component]]