DDCB and FDCB-prefixed instructions only increment the R register twice. [https://stackoverflow.com/questions/8540518/z80-memory-refresh-register#comment25506533_16222002 Source]
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== Optimization ==
* RLA, RRA, RLCA, RRCA are essentially optimized versions of RL A, RR A, RLC A, RRC A.
* Many programs use XOR A to set A to zero, since it's one byte smaller and one M-cycle faster than LD A,0.
* Likewise, many programs use AND A or OR A to check if A is zero, since it's also one byte smaller and one M-cycle faster than CP 0.
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* While the syntax of the 8-bit ADD, ADC and SBC instructions all explicitly mention the A register, the SUB instruction does not mention it. On the Zilog eZ80, the SUB instruction explicitly mention the A register.
* The Z80 has a lot of 8-bit registers but it can only really do arithmetic on one of them, A.
* RLA, RRA, RLCA, RRCA are optimized versions of RL A, RR A, RLC A, RRC A.
* Many programs use XOR A to set A to zero, since it's one byte smaller and one M-cycle faster than LD A,0.
* Likewise, many programs use AND A or OR A to check if A is zero, since it's also one byte smaller and one M-cycle faster than CP 0.
* IN r,(C) and OUT (C),r instructions syntax is misleading as these instructions actually use the full 16-bit port address contained in BC. On the Zilog eZ80, these instructions are correctly named IN, r,(BC) and OUT (BC),r.
* The Amstrad engineers chose to use the high byte of the address (register B) for chip selection instead of the low byte (register C) in I/O operations. As a result, OTIR / OTDR / INIR / INDR instructions cannot be used on Amstrad CPC for transferring or reading a sequence of values on a port, as these instructions use the B register as a counter.