This is why the EOR instruction effectively takes only 2 cycles.
To be fair, this concept of pipelining only makes sense when we consider full-cycles. With half-cycles in mind, there is no overlap or shortcut happening. It's the other way around. The CPU has to be idle for 1 half-cycle when the preceding instruction finished with a write access to memory on ϕ2 so that it can fetch the next opcode on next ϕ2 cycle.
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