CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.
=== Overscan bits ===
It's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'
<br>
== HSYNC and VSYNC ==
On CPC, HSYNC and VSYNC from the CRTC are passed to the [[Gate Array]] for further modification. See its wiki page.
The HSYNC width value is interpreted differently between CRTCs. On CRTCs 0/1, if 0 is programmed no HSYNC is generated. On CRTCs 2/3/4, if 0 is programmed this gives a HSYNC width of 16.
CRTCs 1/2 have a fixed VSYNC width value of 16. VSYNC width can be configured with Register 3 R3 on CRTCs 0/3/4. If 0 is programmed this gives 16 lines of VSYNC. The HSYNC and VSYNC signals from the CRTC are passed to the [[Gate Array]] for further modification. See its wiki page. Even if the number of lines of VSYNC is set to 1 in R3, the Gate Array (or ASIC) will output black for 26 lines, including 4 lines of C-VSYNC to the monitor. This is also true if the duration of the CRTC VSYNC is reduced to 2 µseconds.
The bit 0 Bit0 of port B of the PPI changes is directly connected to 1 as soon as the VSYNC signal is produced by pin of the CRTC.
<br>
On CRTC 1, registers 18-30 read as 0, register 31 reads as 0xff.
Details about Reg. 12 and Reg. 13 specifically:
.------- REG 12 --------. .------- REG 13 --------.
| | | |
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
.--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--.
|X |X | | | | | | | | | | | | | | | |
'--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--'
'--.--'--.--'---------------.-----------------'
| | |
| | '------> Offset for setting
| | videoram
| | (1024 positions)
| | Bits 0..9
| |
| '-------------------------> Video Buffer : note (1)
|
'-------------------------------> Video Page : note (2)
note (1) note (2)
.--.--.--------------. .--.--.---------------.
|11|10| Video Buffer | |13|12| Video Page |
|--|--|--------------| |--|--|---------------|
| 0| 0| 16Ko | | 0| 0| 0000 - 3FFF |
|--|--|--------------| |--|--|---------------|
| 0| 1| 16Ko | | 0| 1| 4000 - 7FFF |
|--|--|--------------| |--|--|---------------|
| 1| 0| 16Ko | | 1| 0| 8000 - BFFF |
|--|--|--------------| |--|--|---------------|
| 1| 1| 32Ko | | 1| 1| C000 - FFFF |
'--'--'--------------' '--'--'---------------'
So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
<br>
* On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.
* CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split-screen , hardware soft scroll and 8-bit printer port functionalities specific to the ASIC.
* See the document "Extra CPC Plus Hardware Information" for more details.
|}
No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. A buffer MA' is needed because MA has to be reloaded at each the beginning of every raster line start.
<br>
=== MA reload ===
R12On CRTCs 0/R13 is loaded only once per 3/4, at the beginning of the first raster line of the frame, in MA and MA'are loaded with R12/R13. Otherwise, MA is loaded with MA'. On CRTC 2, at the first beginning of every raster line start of the frame. The counter (including the first one), MA is then reloaded loaded with the value of MA' . On CRTC 1, at each the beginning of every raster line start. And at each new of the first character line startof the frame (ie. when VCC=0), MA' captures the current value is loaded with R12/R13 instead of MA'.This discrepancy is a major source of incompatibility if the programmer does not take care. In demos and games, to be compatible with all CRTCs, program R12/R13 when VCC!=0. This will then take effect at the next frame start. <br> === MA buffering ===
The exception is At the CRTC 1 for which MA is reloaded at each end of the display of the last raster line start with R12/R13 instead of each character line (ie. when HCC=R1 and VLC=R9), MA' as long as VCC=0captures the current value of MA.
This CRTC 2 is a major source the exception: at the end of incompatibility if the programmer does not take care display of this discrepancy. In demos and gamesthe last raster line of the frame, to make a display compatible with all CRTCs, program MA' captures R12/R13 when VCC!=0. This will then take effect at the next frame startinstead of MA.
<br>
=== VSC (C3h) overflow ===
During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will continue to count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.
On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.
=== HSC (C3l) overflow ===
During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will continue to count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.
The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.
On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will continue to count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame
During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will continue to count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end