Changes

PAL16L8

21 bytes added, 11 May
[[File:Amstrad6128.jed]] Original JED File posted on CPCWiki Forum
 
== PAL I/O port ==
 
Bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1, 2. It can be at 0 or 1 on CRTCs 3 and 4.
 
For compatibility reasons, it is strongly advised to always set bit 14 to 1 to select PAL.
 
See [https://www.cpcwiki.eu/forum/news-events/release-of-amstrad-cpc-crtc-compendium-and-amazing-demo-rev-2021/msg239536 Discussion on the forum]
== See also ==
*For RAM banking settings see Register 3 of the [[Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address).
 
*Bit 14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0, 1, 2. It can be at 0 or 1 on CRTCs 3 and 4. For compatibility reasons, it is strongly advised to always set bit 14 to 1 to select PAL. See [https://www.cpcwiki.eu/forum/news-events/release-of-amstrad-cpc-crtc-compendium-and-amazing-demo-rev-2021/msg239536 Discussion on the forum]
*CPC 464/664 cannot deal with A14/A15 for bank 0 like the 6128 does. External RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]
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