=== VRAM ===
* VRAM read/write via registers, 0,1,2 and 3,4,5 and port 0 use *logical* addresses and not physical addresses. Writing in one mode, and then reading back in another can yield data in a different order because the addresses are translated from logical to physical based on the mode.
* In terms of physical addresses, if you consider physical address 0-&3ffff to be VRAM0 and physical address &40000-&7ffff to be VRAM1, then in P1 mode, the physical address equals logical address and in bitmap modes, every even address maps to &0-&3ffff (every even is VRAM0) and every odd address maps to &40000-&7ffff (VRAM 1). This is described in the PDF.