2. The attributes for each sprite take 8 bytes. Each attribute block has the following format:
{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Length''||''Description'' |-|0||2||Sprite X (see note)|-|2||2||Sprite Y (see note)|-|4||1||Sprite Magnification (see note)|-|5-7||3||unused (0)|-|}
Note: the Sprite X, Y and magnification are in the same order as the ASIC registers
6. The attributes for each DMA channel take 4 bytes. Each attribute block has the following format:
{|{{Prettytable|width: 700px; font-size: 2em;}}|''Offset (Hex)''||''Length''||''Description'' |-|0||2||DMA Channel address (see note)|-|2||1||DMA Channel prescalar (see note)|-|3||1||unused (0)|-|}
Note: the DMA address and prescalar are in the same order as the ASIC registers.
7 These registers are internal to the CPC+ and define the current DMA operation:
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Offset (Hex)''||''Length''||''Description''
|-
|0||2||loop counter (note a)
|-
|2||2||loop address (note b)
|-
|4||2||pause count (note c)
|-
|6||1||pause prescalar count (note d)
|-
|}
a. This value represents the number of loops remaining. 0 = none. This count is between 0..0FFF. This counter counts down.
10. This value represents the current unlock sequence state.
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''State ID''||''Synchronised State''||''Note''
|-
|0||Not synchronised||ASIC is waiting for first non-zero byte to be written, this is the first synchronisation byte required
|-
|1||Not synchronised||ASIC is waiting for zero byte to be written, this is the second synchronisation byte required
|-
|2..10||synchronised||ASIC is waiting for byte from unlock sequence. e.g. if "2", ASIC is waiting for &FF, the first byte of the unlock sequence. if "3" ASIC is waiting for &77, the second byte of the unlock sequence.
|-
|}