Changes
=== CPC+ Chunk ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|''Offset (Hex)''||''Length''||''Addr in ASIC register-ram''||''Description''
|-
|000-7FF||800||4000-4FFF||Sprite Bitmaps (note 1)
|-
|800-87F||8*16||6000-607F||Sprite Attributes (see below) (note 2)
|-
|880-8BF||32*2||6400-643F||Palettes (note 3)
|-
|8C0||1||6800||Programmable Raster Interrupt (note 4)
|-
|8C1||1||6801||Screen split scan-line (note 4)
|-
|8C2||2||6802-6803||Screen split secondary screen-address (note 4)
|-
|8C4||1||6804||Soft scroll control register (note 4)
|-
|8C5||1||6805||Interrupt vector (note 4)
|-
|8C6-8C7||2||-||unused (0)
|-
|8C8-8CF||8||6808-680f||Analogue input channels 0-7 (note 5)
|-
|8D0-8DB||3*4||6C00-6C0B||Sound DMA channel attributes 0-2 (see below) (note 6)
|-
|8DC-8DE||3||-||unused (0)
|-
|8DF||1||6C0F||DMA Control/Status (note 4)
|-
|8E0-8F4||3*7||Internal||DMA channel 0-2 internal registers (see below) (note 7)
|-
|8F5||1||Internal||gate array A0 register value (note 8)
|-
|8F6||1||Internal||gate array A0 lock: 0=locked, 1=unlocked (note 9)
|-
|8F7||1||Internal||ASIC unlock sequence state (note 10)
|-
|}
=== Notes ===
1. The sprite data is packed, with two sprite pixels per byte. Bits 7..4 define the first pixel and bits 3..0 define the second pixel.
2. The attributes for each sprite take 8 bytes. Each attribute block has the following format:
Note: the Sprite X, Y and magnification are in the same order as the ASIC registers
3. This is a direct copy of the palette in CPC+ ASIC Ram. There are 32 colours each with 2-bytes per colour.
4. These bytes in the snapshot represent the last value written to these ASIC registers.
5. These bytes represent the inputs to the analogue channels.
6. The attributes for each DMA channel take 4 bytes. Each attribute block has the following format:
Note: the DMA address and prescalar are in the same order as the ASIC registers.
7 These registers are internal to the CPC+ and define the current DMA operation:
a. This value represents the number of loops remaining. 0 = none. This count is between 0..0FFF. This counter counts down.
b. This is the Amstrad memory address to loop back to. It is a pointer to the DMA instruction after the last REPEAT instruction.
c. This value represents the pause count and the count is between 0...0FFF. (TO BE CHECKED: down counter? what exactly does it represent)
d. This value represents the pause prescalar count and the count is between 0..FF. (TO BE CHECKED: down counter? what exactly does
it represent)
8. This value represents the last value written to this I/O port.
9. This value represents the lock status of the ASIC. If the ASIC is un-locked then the advanced features and ASIC registers are accessible.
10. This value represents the current unlock sequence state.
