The explanation above is just an approximation. Latest research on the subject (May 2024) show that '''SCF/CCF instructions are unstable'''. [https://github.com/hoglet67/Z80Decoder/wiki/Unstable-CCF-SCF-Behaviour Source]
|-
| IR (Instruction Register) || 8-bit || Holds the opcode of the currently executing instruction || Internally used, not accessible by the programmer. Not to be confused with I (Interrupt Vector) and R (Memory Refresh) registers.
|-
| EIP (Extended Instruction Prefix) || 2-bit || Holds the prefix for extended instructions (CB, ED, or none) || Used for extended instruction sets like bitwise ops.
|-
| IMP (Indexing Mode Prefix) || 2-bit || Specifies the indexing mode (DD for IX+d, FD for IY+d, or none for HL) || Indicates use of index registers (IX or IY) for memory access.
|}