== DMA sound channels ==
Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially.
These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).
The available commands are:
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).
Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially.
All instructions execute in 1 cycle, except LOAD which requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the PPI, or 2 extra cycles if the CPU access was itself a PSG register write.