Changes

PAL16L8

269 bytes removed, 5 July
/* PAL MMR register */
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the [[Gate Array]] can only access the Base 64k page of RAM.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|!colspan=2|'''MMR'''||!colspan=3|'''64K page'''||'''!S'''||!colspan=2|'''MM'''||!colspan=4 style="text-align: center;"|'''CPU Memory Mapping'''
|-
|'''!7'''|'''!6'''|'''!5'''|'''!4'''|'''!3'''|'''!2'''|'''!1'''|'''!0'''|style="text-align: center;"|'''!&0000-&3fff'''|style="text-align: center;"|'''!&4000-&7fff'''|style="text-align: center;"|'''!&8000-&bfff'''|style="text-align: center;"|'''!&c000-&ffff'''
|-
|1
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