<br>
== Registers == === Register 0 - Palette Index (Pen selection) ===
When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.
Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
<br>
=== Register 1 - Palette Data (Colour selection) ===
Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.
Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
<br>
=== Register 2 - Select screen mode and ROM configuration ===
This is a general purpose register responsible for the [[Video modes|screen mode]] and the ROM configuration.
==== Screen mode selection ====
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}
<br>
=== Register 3 - RAM Banking ===
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.