Changes
/* Controlling the Gate Array */
The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".
The recommended I/O port address is &7Fxx.
The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 the first bits of the data define the function selected (see table below). It is not possible to read from the Gate-Array.
{|{{Prettytable|width: 700px; font-size: 2em;}}
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!colspan=4|''Data Bit 7''8bit command!rowspan=2|Machine!rowspan=2|''Data Bit 6''Register!rowspan=2|Description!rowspan=2|''Function''Chip
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| 0 || 1 0 || x || style="text-align: center;" | n || All || PENR || Select colour for selected pena color register || Gate Array
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| 0 || 1 || 0 x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register || Select screen mode, ROM configuration and interrupt controlGate Array
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| 1 || 1 0 || RAM Memory Management (note 1)0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
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| 1 || 0 || 1 || style="text-align: center;" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
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| 1 || 0 || 1 || style="text-align: center;" | n || Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
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| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || Memory mapping || PAL
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