== PAL I/O port ==
Note that no settings are stored in the Gate Array itself regarding register 3, but (MMR). But the PAL and Gate Array share an I/O port addressso that it appears to be the same chip to the programmer.
Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, 4.
30 IF PEEK(&4000)=&C7 THEN PRINT"PAL chip absent/inactive":END
40 OUT &3FFF,&C7
50 IF PEEK(&4000)=&C7 THEN PRINT"IO Bit14=0 PAL I/O layout Bit 14selected" ELSE PRINT"IO Bit14=0 PAL Selectnot selected":END60 OUT &7F00,&C0:POKE &C000,&C070 OUT &7F00,&C3:POKE &4000,&C3:OUT &7F00,&C080 IF PEEK(&4000C000)=&C0 C3 THEN PRINT"PAL I/O layout Bit 14=0 PAL not selectedValid RAM mode &C3":END70 ELSE PRINT"Error!Invalid RAM mode &C3"
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