== See also ==
*For RAM banking settings see Register 3 of the [[Gate Array]] (Note that no settings are stored in the gate array, but the PAL and gate array share an I/O port address).
*CPC 464/664 cannot deal with A14/A15 for bank 0 like the 6128 does. External RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]