Gate Array

Gate Array

Also designated as Video gate Array (VGA, not to be confused with IBM PC compatible graphic card spec).

The Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.

In the CPC+ system, the functions of the Gate Array are integrated into a single ASIC. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.

In the KC Compact system, the functions of the Gate Array are "emulated" in TTL chips, CIO, and its color translation EPROM.

In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into a ASIC.

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.

The Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array).

Every microsecond:

• The CRTC generates a memory address using it's MA and RA signal outputs. See the CRTC wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
• The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
• The video hardware is given priority so that the display is not disrupted.

The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.

In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.

Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed.

Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80.

Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.

On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.

The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.

The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. Source

The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).

Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). Source

Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.

On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2.

R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:

• When it exceeds 51
• By setting bit4 of the RMR register of the Gate Array to 1
• At the end of the 2nd HSYNC after the start of the VSYNC

When the Gate Array sends an interrupt request:

• If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place
• If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared and the interrupt takes place. This happens only after the instruction that follows EI as this Z80 instruction has a 1-instruction delay.

Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the ASIC wiki page.

The HSYNC and VSYNC signals are received from the CRTC. These signals are then modified by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will be sent to the display.

When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode.

C-HSYNC begins 2µs after activation of the CRTC HSYNC and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included.

On Gate Array, even if the duration of the CRTC VSYNC is reduced to 2 µseconds, the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASIC, the CRTC VSYNC must be active as long as the C-VSYNC signal is sent to the monitor.

The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:

• H06 counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.
• V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour black.

If CRTC VSYNC is activated again while V26 is still in progress, then V26 is reset to 0 and starts counting up again the HSYNC pulses.

The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC.

C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter.

The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".

The recommended I/O port address is &7Fxx.

The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.

The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.

In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.

In the CPC6128, MMR is performed by a PAL located on the main PCB, or an external memory expansion.

In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.

Note: The Plus palette capabilities are only accessible through the ASIC I/O page. Registers PENR and INKR are not needed in that case.

Register PENR (Select a color register)

When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.

The pen remains selected until another is chosen.

Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.

Summary

Register INKR (Change the value of the currently selected color register)

Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.

Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.

Summary

Register RMR (Control Interrupt counter, ROM mapping and Graphics mode)

This is a general purpose register responsible for the graphics mode and the ROM configuration.

Graphics mode selection

The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.

• Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the KC Compact (which outputs black in Mode 3).

Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.

ROM configuration selection

Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.

Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on upper rom selection for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.

Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.

Summary

Register RMR2 (ASIC & Advanced ROM mapping)

This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked.

The lower ROM address and ASIC I/O page modes are:

 -Mode-   ROM address    ASIC I/O Page
   00     &0000-&3FFF      Disabled
   01     &4000-&7FFF      Disabled
   10     &8000-&BFFF      Disabled
   11     &0000-&3FFF     &4000-&7fff

The physical ROMs are also accessible as upper ROMs by using the Upper ROM Bank Number port and the RMR register.

Register MMR (RAM memory mapping)

This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with Standard Memory Expansions). Note: In the CPC 6128, the register is a separate PAL chip that assists the Gate Array chip. See its wiki page.

The 3bit RAM Config value is used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:

 -Address-     0      1      2      3      4      5      6      7
 0000-3FFF   RAM_0  RAM_0  RAM_4  RAM_0  RAM_0  RAM_0  RAM_0  RAM_0
 4000-7FFF   RAM_1  RAM_1  RAM_5  RAM_3  RAM_4  RAM_5  RAM_6  RAM_7
 8000-BFFF   RAM_2  RAM_2  RAM_6  RAM_2  RAM_2  RAM_2  RAM_2  RAM_2
 C000-FFFF   RAM_3  RAM_7  RAM_7  RAM_7  RAM_3  RAM_3  RAM_3  RAM_3

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

Defining the colours,
Setting pen 0 to Bright White.

LD BC,7F00 ;Gate Array port
LD A,%00000000+0 ;Pen number (and Gate Array function)
OUT (C),A ;Send pen number
LD A,%01000000+11 ;Pen colour (and Gate Array function)
OUT (C),A ;Send it
RET

Setting the mode and ROM configuration, 
Mode 2, upper and lower ROM disabled.

LD BC,7F00 ;Gate array port
LD A,%10000000+%00001110 ;Mode and ROM selection (and Gate Array function)
OUT (C),A ;Send it
RET

Misc

The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.

Note

The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the colour will remain.

Example: [For whatever reason, this example does NOT refer to the above firmware stuff]

ld bc,7f00+1 ;Gate array function (set pen)
;and pen number
out (c),c
ld bc,7f00 ;41 
;Gate array function (set colour)
;and colour number
out (c),c
ret

On the CPC, split rasters occur halfway (after the 8th mode2 pixel) through the rendering of a CRTC character.

On Amstrad Plus, split rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour.

To display a CPC image you will need to use a analogue monitor with a composite sync.

Palette sorted by Hardware Colour Numbers

Palette sorted by Firmware Colour Numbers

Intensities

The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).

On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by Grim and independently confirmed by Nocash. Source

• CPC Palette - some more details

This explains why the Amstrad engineers used these values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:

• 0% became #0
• 50% became #6
• 100% became #F

They specifically chose #6 for the 50% value instead of #7, to better match the real Amstrad CPC palette.

Green Screen Colours

On a green screen (where all colours are shades of unsaturated green), the colours (in BASIC colours) are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to Mark Rison for this information)

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values.

Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

To calculate the luminance value

Red

0% => do not add anything

50% => add 3

100% => add 6

Green

0% => do not add anything

50% => add 9

100% => add 18

Blue

0% => do not add anything

50% => add 1

100% => add 2

• 

  40010 GA Metal Layer

• 

  40010 GA with Metal Layer removed

• 

  40226 PreASIC Metal Layer

Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. Source

• Electronic signals analysis of the Gate Array by Bread80
• Gate Array documentation from Grimware
• Quasar Gate Array documentation (in french)

• Gate Array and ASIC Pin-Outs
• PAL16L8 : for RAM arrangement
• ASIC : for Plus users

• CRTC : the other video stuff
• Synchronising with the CRTC and display : technical details on the relationship between Gate Array and CRTC.

• Video modes : for other informations on colours and pixels.

• Media:40010-simplified V03.pdf Forum thread Gate Array schematics - reverse engineered by Gerald