Default I/O Port Summary

This list shows only the internal standard I/O ports, as used in the BIOS ROM of the CPC 464/664/6128 BIOS, and in the AMSDOS ROM of the CPC 664/6128 and DDI-1. For a more complete list, including all Peripherals, see the Complete I/O Port Summary.

I/O Ports

I/O	Decoded as	Port	Read	Write
#7FXX	%01xxxxxx xxxxxxxx	Gate Array	-	Write
#7FXX	%0xxxxxxx xxxxxxxx	PAL extension to Gate Array for 128K RAM banking	-	Write
#BCXX	%x0xxxx00 xxxxxxxx	6845 CRTC Index	-	Write
#BDXX	%x0xxxx01 xxxxxxxx	6845 CRTC Data Out	-	Write
#BEXX	%x0xxxx10 xxxxxxxx	6845 CRTC Status (as far as supported)	Read	-
#BFXX	%x0xxxx11 xxxxxxxx	6845 CRTC Data In (as far as supported)	Read	-
#DFXX	%xx0xxxxx xxxxxxxx	Upper ROM Bank Number	-	Write
#EFXX	%xxx0xxxx xxxxxxxx	Printer Port	-	Write
#F4XX	%xxxx0x00 xxxxxxxx	8255 PPI Port A (PSG Data)	Read	Write
#F5XX	%xxxx0x01 xxxxxxxx	8255 PPI Port B (Vsync,PrnBusy,Tape,etc.)	Read	-
#F6XX	%xxxx0x10 xxxxxxxx	8255 PPI Port C (KeybRow,Tape,PSG Control)	-	Write
#F7XX	%xxxx0x11 xxxxxxxx	8255 PPI Control-Register	-	Write
#F8FF	N/A	Peripheral Soft Reset (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF)	-	Write
#FA7E	%xxxxx0x0 0xxxxxxx	Floppy Motor Control (for 765 FDC)	-	Write
#FADC	%xxxxx0x0 xx0xxx00	Amstrad Serial Interface Z80-SIO / DART port A Data Register	Read	Write
#FADD	%xxxxx0x0 xx0xxx01	Amstrad Serial Interface Z80-SIO / DART port A Control Reg.	Read	Write
#FADE	%xxxxx0x0 xx0xxx10	Amstrad Serial Interface Z80-SIO / DART port B Data Register	Read	Write
#FADF	%xxxxx0x0 xx0xxx11	Amstrad Serial Interface Z80-SIO / DART port B Control Reg.	Read	Write
#FB7E	%xxxxx0x1 0xxxxxx0	765 FDC (internal) Status Register	Read	-
#FB7F	%xxxxx0x1 0xxxxxx1	765 FDC (internal) Data Register	Read	Write
#FBDC	%xxxxx0x1 xx0xxx00	Amstrad Serial Interface 8253 Timer counter 0	Read	Write
#FBDD	%xxxxx0x1 xx0xxx01	Amstrad Serial Interface 8253 Timer counter 1	Read	Write
#FBDE	%xxxxx0x1 xx0xxx10	Amstrad Serial Interface 8253 Timer counter 2	Read	Write
#FBDF	%xxxxx0x1 xx0xxx11	Amstrad Serial Interface 8253 Timer Modus Select	-	Write

• The three 765 FDC floppy ports are contained in CPC 664/6128/Plus and DDI-1 only.

• The eight Amstrad Serial Interface ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.

• Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.

• As components use partial address decoding, it is therefore possible to send the same value to different components simultaneously by carefully using custom I/O ports.

Memory Mapped I/O Ports

Mem	Decoded as	Port	Read	Write
#4000-7FFF	%01xxxxxx xxxxxxxx	ASIC - CPC+/GX4000 registers	Read	Write

The ASIC I/O page is defined as follows:

ADDR	SIZE	POR	TYPE	MNEM	USE
4000h	100h	N	R/W		Sprite 0 image data
4100h	100h	N	R/W		Sprite 1 image data
...	...	...	...	...	...
4F00h	100h	N	R/W		Sprite 15 image data
Block unused
6000h	2	N	R/W	X0	Sprite 0 X position
6002h	2	N	R/W	Y0	Sprite 0 Y position
6004h	1	Y	W	M0	Sprite 0 magnification
6005h	3				(unused)
6008h	2	N	R/W	X1	Sprite 1 X position
600Ah	2	N	R/W	Y1	Sprite 1 Y position
600Ch	1	Y	W	M1	Sprite 1 magnification
600Dh	3				(unused)
...	...	...	...	...	...
6078h	2	N	R/W	X15	Sprite 15 X position
607Ah	2	N	R/W	Y15	Sprite 15 Y position
607Ch	1	N	W	M15	Sprite 15 magnification
607Dh	3				(unused)
Block unused
6400h	2	N	R/W		Colour palette, pen 0
6402h	2	N	R/W		Colour palette, pen 1
...	...	...	...	...	...
641Eh	2	N	R/W		Colour palette, pen 15
6420h	2	N	R/W		Colour palette, border
6422h	2	N	R/W		Colour palette, sprite colour 1
6424h	2	N	R/W		Colour palette, sprite colour 2
...	...	...	...	...	...
643Eh	2	N	R/W		Colour palette, sprite colour 15
Block unused
6800h	1	Y	W	PRI	Programmable raster interrupt scan line
6801h	1	Y	W	SPLT	Screen split scan line
6802h	2	N	W	SSA	Screen split secondary start address
6804h	1	Y	W	SSCR	Soft scroll control register
6805h	1	N	W	IVR	Interrupt Vector (Bit 0 set to 1 on reset)
6806h	2				(unused)
6808h	1		R	ADC0	Analogue input channel 0
6809h	1		R	ADC1	Analogue input channel 1
680Ah	1		R	ADC2	Analogue input channel 2
680Bh	1		R	ADC3	Analogue input channel 3
680Ch	1		R	ADC4	Analogue input channel 4
680Dh	1		R	ADC5	Analogue input channel 5
680Eh	1		R	ADC6	Analogue input channel 6
680Fh	1		R	ADC7	Analogue input channel 7
Block unused
6C00h	2	N	W	SAR0	"DMA" channel 0 address pointer
6C02h	1	N	W	PPR0	"DMA" channel 0 pause prescaler
6C03h	1				(unused)
6C04h	2	N	W	SAR1	"DMA" channel 1 address pointer
6C06h	1	N	W	PPR1	"DMA" channel 1 pause prescaler
6C07h	1				(unused)
6C08h	2	N	W	SAR2	"DMA" channel 2 address pointer
6C0Ah	1	N	W	PPR2	"DMA" channel 2 pause prescaler
6C0Bh	4				(unused)
6C0Fh	1	Y	R/W	DCSR	"DMA" control/status register
Block unused

POR column indicates whether a register has power on reset. A "N" indicates that the contents of a register are undefined at power on.

There is only one pixel per byte in sprite image data (bits3..0 of each byte define the palette index for this pixel, bits7..4 are ignored)

Sprite magnification is coded in 1 byte:

• bits7..3 are ignored
• bits3..2 are X magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4)
• bits1..0 are Y magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4)

A colour in the palette is coded in 2 bytes:

• For first byte, bits7..4 are blue value, bits3..0 are red value
• For second byte, bits7..4 are ignored, bits3..0 are green value

Internal Links

• Arnold V specs
• Arnold V Specs Revised