Difference between revisions of "8253 chip"
(Created page with '== Usage in CPC interfaces == Used by standard Amstrad (and compatible) RS232 interfaces, mapped to Ports: FBDCh Amstrad RS323 8253 Baudrate Time…') |
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== Usage in CPC interfaces == | == Usage in CPC interfaces == | ||
| − | Used by standard [[ | + | Used by standard [[Amstrad Serial Interface]] (and compatible) RS232 interfaces, mapped to Ports: |
FBDCh Amstrad RS323 8253 Baudrate Timer 0 Channel A TX Clock (R/W) | FBDCh Amstrad RS323 8253 Baudrate Timer 0 Channel A TX Clock (R/W) | ||
| Line 7: | Line 7: | ||
FBDEh Amstrad RS323 8253 Baudrate Timer 2 Channel B RX/TX Clock (R/W) | FBDEh Amstrad RS323 8253 Baudrate Timer 2 Channel B RX/TX Clock (R/W) | ||
FBDFh Amstrad RS323 8253 Baudrate Timer 0-2 Control Registers (W) | FBDFh Amstrad RS323 8253 Baudrate Timer 0-2 Control Registers (W) | ||
| − | Clock Input seems to be 2MHz, Clock output goes to a Z80 DART chip, | + | Clock Input seems to be 2MHz, Clock output goes to a [[Z80-DART/Z80-SIO chip]], |
Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip | Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip | ||
| − | Also used by [[KDS_Electronics_Serial_Interface|KDS | + | Also used by [[KDS_Electronics_Serial_Interface|KDS Serial Interface]], mapped to other Ports, and RX/TX exchanged: |
FBE8h KDS RS232 8253 Baudrate Timer 0 (RX Clock) (R/W) | FBE8h KDS RS232 8253 Baudrate Timer 0 (RX Clock) (R/W) | ||
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FBEAh KDS RS232 8253 Baudrate Timer 2 (not used) (R/W) | FBEAh KDS RS232 8253 Baudrate Timer 2 (not used) (R/W) | ||
FBEBh KDS RS232 8253 Baudrate Timer 0-2 Control Registers (W) | FBEBh KDS RS232 8253 Baudrate Timer 0-2 Control Registers (W) | ||
| − | Clock Input seems to be 2MHz, Clock output goes to a 6850 chip, | + | Clock Input seems to be 2MHz, Clock output goes to a [[6850 ACIA chip]], |
Clock Output may be further divided by 1, 16, or 64 in the 6850 chip | Clock Output may be further divided by 1, 16, or 64 in the 6850 chip | ||
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6=Same as Mode 2 | 6=Same as Mode 2 | ||
7=Same as Mode 3 | 7=Same as Mode 3 | ||
| − | |||
0 BCD (0=normal, 1=bcd) | 0 BCD (0=normal, 1=bcd) | ||
When used as RS232 Baudrate Generator (ie. as in the CPC), all three registers should be set to square-wave non-bcd lsb-then-msb (ie. write values 36h, 76h, and B6h to this port). | When used as RS232 Baudrate Generator (ie. as in the CPC), all three registers should be set to square-wave non-bcd lsb-then-msb (ie. write values 36h, 76h, and B6h to this port). | ||
Revision as of 18:09, 8 January 2010
Usage in CPC interfaces
Used by standard Amstrad Serial Interface (and compatible) RS232 interfaces, mapped to Ports:
FBDCh Amstrad RS323 8253 Baudrate Timer 0 Channel A TX Clock (R/W) FBDDh Amstrad RS323 8253 Baudrate Timer 1 Channel A RX Clock (R/W) FBDEh Amstrad RS323 8253 Baudrate Timer 2 Channel B RX/TX Clock (R/W) FBDFh Amstrad RS323 8253 Baudrate Timer 0-2 Control Registers (W) Clock Input seems to be 2MHz, Clock output goes to a Z80-DART/Z80-SIO chip, Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip
Also used by KDS Serial Interface, mapped to other Ports, and RX/TX exchanged:
FBE8h KDS RS232 8253 Baudrate Timer 0 (RX Clock) (R/W) FBE9h KDS RS232 8253 Baudrate Timer 1 (TX Clock) (R/W) FBEAh KDS RS232 8253 Baudrate Timer 2 (not used) (R/W) FBEBh KDS RS232 8253 Baudrate Timer 0-2 Control Registers (W) Clock Input seems to be 2MHz, Clock output goes to a 6850 ACIA chip, Clock Output may be further divided by 1, 16, or 64 in the 6850 chip
Timer Registers
8253 Timer 0 Register (R/W) 8253 Timer 1 Register (R/W) 8253 Timer 2 Register (R/W) These ports allow to access three decrementing 16bit timers. Assuming that the corresponding Control Registers are set to "LSB-then-MSB", the 16bit reload values (aka divider values) are written in two 8bit fractions:
1st write: LSB of reload value 2nd write: MSB of reload value
For the CPC RS232 interfaces, the baudrates are calculated as such:
Baudrate = 2MHz / reload / prescaler
Where "prescaler" is an additional divider in the DART or 6850 chip. Eg.
300 baud = 2MHz / 01A0h / 16 9600 baud = 2MHz / 000Dh / 16
Note: Reading from the Timer registers does probably return the current counter values rather than the reload value (?) also not sure if/how it freezes between LSB and MSB reads, and how Control bits 4-5 are working exactly.
Control Registers
8253 Timer 0-2 Control Registers (W) This port allows to configure three write-only 6bit registers: Bit6-7 specify which of the registers is to be updated, Bit0-5 contain the new value for that register.
7-6 Counter Number (0..2=Counter 0..2, 3=Reserved)
5-4 Read/Load (0=Latching?, 1=MSB only, 2=LSB only, 3=LSB-then-MSB)
3-1 Mode
0=Interrupt on Terminal Count
1=Programmable One-Shot
2=Rate Generator (short edge, low for 1 period of input clock)
3=Rate Generator (square wave, low for 2nd half of counter range)
4=Software Triggered Strobe
5=Hardware Triggered Strobe
6=Same as Mode 2
7=Same as Mode 3
0 BCD (0=normal, 1=bcd)
When used as RS232 Baudrate Generator (ie. as in the CPC), all three registers should be set to square-wave non-bcd lsb-then-msb (ie. write values 36h, 76h, and B6h to this port).
