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== M-cycles and T-states == In the Z80, M-cycles represent high-level execution cycles for an instruction, while T-states are individual clock cycles. Each M-cycle consists of several T-states, and instructions require one or more M-cycles. M-cycles can be classified as follows:* Opcode Fetch (aka M1 cycle): this is always the first (and sometimes only) machine cycle in an instruction (4 clock cycles)* Memory Read: read a byte from memory (3 clock cycles)* Memory Write: write a byte to memory (3 clock cycles)* IO Read: read a byte from an IO port (4 clock cycles)* IO Write: write a byte to an IO port (4 clock cycles)* Interrupt Acknowledge: these are special machine cycles which are executed at the start of maskable interrupt handling* Extra: many instructions contain extra clock cycles necessary for computations. In the official CPU documentation, these are sometimes identified as separate machine cycles, and sometimes just lumped together with other machine cycle types. <br> == CPC Timings ==
On CPC, bus arbitration is done on every CPU bus access. On MSX, bus arbitration only applies to M1 machine cycles but access to VRAM has other limitations. On ZX Spectrum, bus arbitration is done not by using the /WAIT pin but by disabling the CPU clock when needed.