Changes
Z80
,/* The Decode ROM (PLA) */
Two counters are set up in parallel. One counting the Memory (or Machine) states (M1..M5), the other Time states (T1..T5) within (*1). With a new instruction the M counter gets reset to 1, with each M state the T counter gets reset.
The second stage of instruction decode is something that is much like another PLA, but built out of single gates (*2). The gates are set up much like a grid with the timing signals (M1..M5 & T1..T5) as horizontal input and the PLA output (instructions/instruction groups) as vertical input. The gate is built along the vertical line and combining its signal with one or more timing signals using AND/NOR logic (*3). The output of these gates again are fed into the discrete logic of the execution units. [https://retrocomputing.stackexchange.com/questions/6656/how-was-microcode-implemented-in-retro-processors Source]
*1 - this internal structure is also the reason for this otherwise unusual notation used throughout all Z80 documentation.
