* While the syntax of ADD, ADC and SBC instructions all explicitely mention the A register, the SUB instruction does not mention it
* The 16-bit commands ADD HL,ss, ADC HL,ss and SBC HL,ss exist but not the command SUB HL,ss
* The BIT b,(HL) instruction exposes certain bits of the internal register WZ to the undocumented flags F5 and F3
* The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.
* Instructions IN r,(C) and OUT (C),r surprisingly take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access.