Difference between revisions of "Default I/O Port Summary"

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The [[ASIC]] I/O page is defined as follows:
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See the [[ASIC]] page for details.
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{| class="wikitable"
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! ADDR
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! SIZE
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! POR
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! TYPE
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! MNEM
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! USE
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| 4000h || 100h || N || R/W || || Sprite 0 image data
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| 4100h || 100h || N || R/W || || Sprite 1 image data
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| ...  || ...  || ... || ...  || ... || ...
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| 4F00h || 100h || N || R/W || || Sprite 15 image data
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|style="background:#efefef;" colspan="6"|''Block unused''
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| 6000h || 2    || N || R/W  || X0  || Sprite 0 X position
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| 6002h || 2    || N || R/W  || Y0  || Sprite 0 Y position
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| 6004h || 1    || Y || W    || M0  || Sprite 0 magnification
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| 6005h || 3    ||  ||      ||    || (unused)
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| 6008h || 2    || N || R/W  || X1  || Sprite 1 X position
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| 600Ah || 2    || N || R/W  || Y1  || Sprite 1 Y position
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| 600Ch || 1    || Y || W    || M1  || Sprite 1 magnification
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| 600Dh || 3    ||  ||      ||    || (unused)
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| ...  || ...  || ... || ...  || ... || ...
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| 6078h || 2    || N || R/W  || X15 || Sprite 15 X position
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| 607Ah || 2    || N || R/W  || Y15 || Sprite 15 Y position
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| 607Ch || 1    || N || W    || M15 || Sprite 15 magnification
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| 607Dh || 3    ||  ||      ||    || (unused)
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|style="background:#efefef;" colspan="6"|''Block unused''
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| 6400h || 2    || N || R/W  ||    || Colour palette, pen 0
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| 6402h || 2    || N || R/W  ||    || Colour palette, pen 1
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| ...  || ...  || ... || ...  || ... || ...
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| 641Eh || 2    || N || R/W  ||    || Colour palette, pen 15
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| 6420h || 2    || N || R/W  ||    || Colour palette, border
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| 6422h || 2    || N || R/W  ||    || Colour palette, sprite colour 1
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| 6424h || 2    || N || R/W  ||    || Colour palette, sprite colour 2
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| ...  || ...  || ... || ...  || ... || ...
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| 643Eh || 2    || N || R/W  ||    || Colour palette, sprite colour 15
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|style="background:#efefef;" colspan="6"|''Block unused''
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| 6800h || 1    || Y || W    || PRI  || Programmable raster interrupt scan line
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| 6801h || 1    || Y || W    || SPLT || Screen split scan line
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| 6802h || 2    || N || W    || SSA  || Screen split secondary start address
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| 6804h || 1    || Y || W    || SSCR || Soft scroll control register
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| 6805h || 1    || N || W    || IVR  || Interrupt Vector (Bit 0 set to 1 on reset)
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| 6806h || 2    ||  ||      ||    || (unused)
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| 6808h || 1    ||  || R    || ADC0 || Analogue input channel 0
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| 6809h || 1    ||  || R    || ADC1 || Analogue input channel 1
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| 680Ah || 1    ||  || R    || ADC2 || Analogue input channel 2
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| 680Bh || 1    ||  || R    || ADC3 || Analogue input channel 3
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| 680Ch || 1    ||  || R    || ADC4 || Analogue input channel 4
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| 680Dh || 1    ||  || R    || ADC5 || Analogue input channel 5
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| 680Eh || 1    ||  || R    || ADC6 || Analogue input channel 6
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| 680Fh || 1    ||  || R    || ADC7 || Analogue input channel 7
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|style="background:#efefef;" colspan="6"|''Block unused''
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| 6C00h || 2    || N || W    || SAR0 || "DMA" channel 0 address pointer
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| 6C02h || 1    || N || W    || PPR0 || "DMA" channel 0 pause prescaler
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| 6C03h || 1    ||  ||      ||    || (unused)
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| 6C04h || 2    || N || W    || SAR1 || "DMA" channel 1 address pointer
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| 6C06h || 1    || N || W    || PPR1 || "DMA" channel 1 pause prescaler
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| 6C07h || 1    ||  ||      ||    || (unused)
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| 6C08h || 2    || N || W    || SAR2 || "DMA" channel 2 address pointer
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| 6C0Ah || 1    || N || W    || PPR2 || "DMA" channel 2 pause prescaler
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| 6C0Bh || 4    ||  ||      ||    || (unused)
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| 6C0Fh || 1    || Y || R/W  || DCSR || "DMA" control/status register
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|style="background:#efefef;" colspan="6"|''Block unused''
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POR column indicates whether a register has power-on reset. A "N" indicates that the contents of a register are undefined at power-on.
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Latest revision as of 06:23, 4 September 2024

This list shows only the internal standard I/O ports, as used in the BIOS ROM of the CPC 464/664/6128 BIOS, and in the AMSDOS ROM of the CPC 664/6128 and DDI-1. For a more complete list, including all Peripherals, see the Complete I/O Port Summary.


I/O Ports

I/O Decoded as Port Read Write
#7FXX %01xxxxxx xxxxxxxx Gate Array - Write
#7FXX %0xxxxxxx xxxxxxxx PAL extension to Gate Array for 128K RAM banking - Write
#BCXX %x0xxxx00 xxxxxxxx 6845 CRTC Index - Write
#BDXX %x0xxxx01 xxxxxxxx 6845 CRTC Data Out - Write
#BEXX %x0xxxx10 xxxxxxxx 6845 CRTC Status (as far as supported) Read -
#BFXX %x0xxxx11 xxxxxxxx 6845 CRTC Data In (as far as supported) Read -
#DFXX %xx0xxxxx xxxxxxxx Upper ROM Bank Number - Write
#EFXX %xxx0xxxx xxxxxxxx Printer Port - Write
#F4XX %xxxx0x00 xxxxxxxx 8255 PPI Port A (PSG Data) Read Write
#F5XX %xxxx0x01 xxxxxxxx 8255 PPI Port B (Vsync,PrnBusy,Tape,etc.) Read -
#F6XX %xxxx0x10 xxxxxxxx 8255 PPI Port C (KeybRow,Tape,PSG Control) - Write
#F7XX %xxxx0x11 xxxxxxxx 8255 PPI Control-Register - Write
#F8FF N/A Peripheral Soft Reset (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF) - Write
#FA7E %xxxxx0x0 0xxxxxxx Floppy Motor Control (for 765 FDC) - Write
#FADC %xxxxx0x0 xx0xxx00 Amstrad Serial Interface Z80-SIO / DART port A Data Register Read Write
#FADD %xxxxx0x0 xx0xxx01 Amstrad Serial Interface Z80-SIO / DART port A Control Reg. Read Write
#FADE %xxxxx0x0 xx0xxx10 Amstrad Serial Interface Z80-SIO / DART port B Data Register Read Write
#FADF %xxxxx0x0 xx0xxx11 Amstrad Serial Interface Z80-SIO / DART port B Control Reg. Read Write
#FB7E %xxxxx0x1 0xxxxxx0 765 FDC (internal) Status Register Read -
#FB7F %xxxxx0x1 0xxxxxx1 765 FDC (internal) Data Register Read Write
#FBDC %xxxxx0x1 xx0xxx00 Amstrad Serial Interface 8253 Timer counter 0 Read Write
#FBDD %xxxxx0x1 xx0xxx01 Amstrad Serial Interface 8253 Timer counter 1 Read Write
#FBDE %xxxxx0x1 xx0xxx10 Amstrad Serial Interface 8253 Timer counter 2 Read Write
#FBDF %xxxxx0x1 xx0xxx11 Amstrad Serial Interface 8253 Timer Modus Select - Write
  • The three 765 FDC floppy ports are contained in CPC 664/6128/Plus and DDI-1 only.
  • The eight Amstrad Serial Interface ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.
  • Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.
  • As components use partial address decoding, it is therefore possible to send the same value to different components simultaneously by carefully using custom I/O ports.


Memory Mapped I/O Ports

Mem Decoded as Port Read Write
#4000-7FFF %01xxxxxx xxxxxxxx ASIC - CPC+/GX4000 registers Read Write

See the ASIC page for details.


Related pages

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