Gate Array Also designated as Video gate Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).
<br>
In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into a an ASIC.
<br>
== DRAM refresh ==
On Amstrad CPC, the Gate Array is responsible for the DRAM refresh , instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM access accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.
The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.
The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytesin half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]
The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter R52 (the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signal.
On all CRTCs, R52 interrupts always start 1µs after the end of an HSYNC. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the CRTC register 3.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditions:
The recommended I/O port address is &7Fxx.
The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]
The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"| 1 || rowspan="2"| 0 || rowspan="2"| 1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| 1 || 0 || 1 || style="text-align: center;" | n || Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL(only with 128KB or RAM expansion)
|}
In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.
In the CPC6128, MMR is performed by a [[PAL16L8|PALchip]] located on the main PCB, or an external memory expansion.
In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAMROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.
Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
=== Register MMR (RAM memory mapping) ===
This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
{| class="wikitable"
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colorscolours|4 MHz|160x200, 20-column text
|-
|1
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|G
|H
|8 pixels in 2 colorscolours|16 MHz|640x200, 80-column text
|-
|3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colorscolours|4 MHz|160x200, 20-column text
|}
=== Palette sorted by Hardware Colour Numbers ===
{| class="FCK__ShowTableBorderswikitable"|-
|-
| ''!Hardware Number||!Firmware Number|| ''!Colour Name'' | ''!R %'' || ''!G %'' || ''!B %'' || ''!ASIC'' || ''!Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| #666|| bgcolor="#808080" |
| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| #66F||bgcolor="#8080ff" |
|}
<br>
=== Intensities ===
The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by Grim and independently confirmed by Nocash. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details
This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F
<br>
=== Palette sorted by Firmware Colour Numbers ===
The firmware colour palette is sorted by luminance value. {| class="FCK__ShowTableBorderswikitable"|-
|-
| ''!Firmware Number'' || ''!Hardware Number'' || ''!Colour Name'' | ''!R %'' || ''!G %'' || ''!B %'' || ''!ASIC'' || ''!Colour''
|-
| 0|| 54h ||Black || 0|| 0|| 0|| #000||bgcolor="#000000"|
|}
<br> === Intensities === The 0%, 50%, and 100% values in Note: We can observe that the above tables official Amstrad names of some colours are a bit silly: "should-bered" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones)is in fact brown, "yellow" is in fact khaki and on the load applied by external hardware (Monitor, or TV set). On an actual Amstrad CPC, the half-intensity colour signal "white" is measured to be closer to 40% rather than the expected 50%. This was verified by Grim and independently confirmed by Nocash. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]* [[CPC Palette]] - some more details This explains why the Amstrad engineers used these values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:* 0% became #0* 50% became #6* 100% became #F They specifically chose #6 for the 50% value instead of #7, to better match the real Amstrad CPC palettein fact grey.
<br>
=== Green Screen Colours ===
On a green screen (, where all colours are shades of unsaturated green), the colours (in BASIC colours) are in order of increasing intensity. Black is very darkdarkest green, and white is bright brightest green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)
The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values.
*[[Gate Array and ASIC Pin-Outs]]
*[[Video modesPAL16L8]] : for other informations on colours and pixels. *[[CRTC]] : the other video stuff.RAM arrangement
*[[ASIC]] : for Plus users
*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
*[[Video modes]] : for other informations on colours and pixels.
*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]