Note that no settings are stored in the Gate Array itself regarding the MMR register. But the PAL and Gate Array share an I/O port address so that it appears to be the same chip to the programmer.
Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, /4. It must be at 1 on CRTCs 0, /1 and /2 (The result is not guaranteed).
For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL. Furthermore, if bit14=0 then CRTC will be selected too.
FurthermoreThe recommended I/O port address is &7Fxx. Moreover, if bit14=0 then CRTC the PAL only respond to I/O Write requests while the Gate Array will be selected toorespond no matter what the Read/Write I/O signal is.[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]
<br>
On a standard 128k machine (unexpanded), bits5..3 are ignored. Page will always be fixed to Page 0.
<br>
=== Page order ===
RAM expansions are not required to conform to any page order. For example, the [[Dk'tronics Silicon Disc]] is a 256k RAM expansion that provides Pages 4 to 7.
RAM expansions can even be at an adjacent address range. For example, the [[Y-MEM]] is a 512k RAM expansion that uses the &7Exx range instead of the usual &7Fxx.
<br>
<br>
== PAL and Pre-ASIC ==
The PAL component is integrated inside the Pre-ASIC chip contains the PAL component internally. But it is disabled by default on the CPC 464.
It is possible to enable it by doing an hardware modification explained in that article: [[Arnold4]]
<br>
== PAL and ASIC compatibility ==
Most The PAL component is integrated inside the ASIC chip. But it is disabled by default on the 464 Plus and GX4000. [https://www.cpcwiki.eu/forum/news-events/announcing-sonic-gx-a-new-episode-of-sonic-the-hedgehog-for-amstrad-gx-4000/msg248436/#msg248436 Source] Besides, most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source]
The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way.
*[https://www.cpc-power.com/index.php?page=detail&num=14940 CRTC3 demo]
*[https://soundtrackerdma.cpcscene.net/doku.php?id=en:download Soundtracker DMA]
<br>
== Signals used for RAM management ==
The following signals are used for RAM management and are available on the expansion connector.
=== RAMDIS ===
(Internal RAM Disable; Input to Internal RAM)
When RAMDIS="1" the internal RAM of the CPC/CPC+/KC Compact is forced inactive.
e.g. a ram-expansion device would use this signal to override the internal RAM selection with the RAM on the device. The internal RAM would be forced inactive, and the RAM on the ram-expansion would be actived.
=== /RAMRD ===
(RAM Read; Output from Gate-Array)
When /RAMRD="0" a ram read operation is active. This signal is generated by the Gate-Array. This signal will be "0" when:
* A15=A14="0" and bit 2 of the Gate-Array rom configuration register is set to 1. (lower ROM disable)
* A15=A14="1" and bit 3 of the Gate-Array rom configuration register is set to 1. (upper ROM disable)
* A15 is not equal to A14.
<br>
== Initial replacement equation (Porchy) ==
The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:
A15OUT = (!X2 & !X1 & A14
== Fixed version (Gerald) ==
Original version from Porchy suffer suffers from a bad handling of the RAMDIS signal. This cause It caused screen artefact when accessing an external extension RAM like XMEMexpansion.
A14OUT = !( !A14
[[File:Amstrad.cpc6128.pal.ga.jpg]]
<br>
== 576KB vs 640KB total ==
Bits 3, 4, 5 allow to define up to 8 pages of 64K for RAM expansion at a given address range in addition to the 64K base RAM. The internal second 64K RAM bank of the CPC 6128 is usually disabled when a RAM expansion is used, as the 64K enhanced RAM in the 6128 would use the same address range (&7Fxx) as the first 64K of the RAM expansion. This gives you 576K of total RAM on a CPC.
However, if the RAM expansion decodes the [[Standard_Memory_Expansions#Extended_1M-4M_Expansions_.28RAM7.2FYarek-style.29|A8 address line]], you can access the internal second RAM bank of the 6128 from another range (&7Exx). The [[X-MEM]] and [[CPC_iRAM#CPC_iRAM.2F640|iRAM/640]] expansions implement this and therefore can provide 640K of total RAM. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/extram-512kb-to-640kb-for-cpc6128-on-one-dip20-chip-slg46533v-dip/msg247763/#msg247763 Source]
<br>
== Related pages ==
*[[media:Programmable Array Logic PAL16L8ACN.pdf|PAL16L8 datasheet]]
*[[Gate Array and ASIC Pin-Outs]]
*[[Standard Memory Expansions]]
[[Category:Hardware]] [[Category:CPC Internal Components]] [[Category:Electronic Component]] [[Category: Memory expansions]][[Category:Programming]] [[Category:Datasheet]]