Changes
/* Interrupt management */
*If interrupts are not authorized, the R52 counter continues to increment, but the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''', bit5 of R52 is cleared and the interrupt takes place
R52 will return to 0on any of these conditions:
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
