Changes
/* Interrupt management */
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter (R52) that counts from 0 to 51, incrementing after each HSYNC signal.
* When it exceeds 51
* By setting bit4 of the RMR register of the Gate Array to 1
* At the end of the 2nd HSYNC after the start of the VSYNC
When the Gate Array sends an interrupt request:
*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared and the interrupt takes place
*If interrupts are not authorized, the R52 counter continues to increment, but the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''', bit5 of R52 is cleared and the interrupt takes place
== Controlling the Gate Array ==
