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==Amstrad Custom custom chips==
The Amstrad CPC used one custom chip: the video [[Gate Array]] (also called VGA – no connection with the Video PC standard).
Latter Later [[CPC]] cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the [[CRTC]].
The Amstrad [[Plus]] included a "second heart" simply referred as the ASIC.
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== Analog joystick == Analog joystick axes are unsigned 6-bit values. Bits7..6 are always 0. <br> == Colour palette == A colour in the palette is coded in 2 bytes:* For first byte, bits7..4 are blue value, bits3..0 are red value* For second byte, bits7..4 are ignored, bits3..0 are green value <br> == Hardware sprites == Sprites are prioritized so that the border has the highest priority, followed by sprites 0 to 15 in sequence, then the main screen data. There is only one pixel per byte in sprite image data. Bits3..0 of each byte define the palette index for this pixel (a value of 0 means transparent colour). Bits7..4 are ignored. Each sprite magnification is coded in 1 byte:* bits7..3 are ignored* bits3..2 are X magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4)* bits1..0 are Y magnification (00 = not displayed, 01 = x1, 10 = x2, 11 = x4) <br> == Soft Scroll scroll ==
The 8-bit register SSCR (at address 6804h) controls soft scrolling by pixels rather than by characters. Setting this register to 0 (the default value at power-up) disables the soft scroll feature. The soft scrolling mechanism affects the entire main screen, regardless of the split screen feature, but does not affect sprites.
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== Split Screen screen ==
The 8-bit register SPLT register (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value at power-up) disables the split screen feature.
The 16-bit register SSA register (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. SSA works similarly to the duo R12/R13 in the CRTC. This configuration and allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screenregardless.
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== Programmable Raster Interrupt raster interrupt ==
The 8-bit memory-mapped register PRI register (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic [[Gate Array]] R52 raster interrupt system instead.
PRI can be reprogrammed as required to produce multiple interrupts per frame.
Additionally, on Amstrad Plus, we have multiple sources of interrupts as each DMA sound channel Also PRI can trigger interrupts beyond the first 256 lines. For example, when PRI = 10, an interruptwill be triggered at line 10 but also at line 266.
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== DMA commands sound channels == Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially. These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).
The available commands are:
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).
Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially.
All instructions execute in 1 cycle, except LOAD which requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the PPI, or 2 extra cycles if the CPU access was itself a PSG register write.
The DMA control and status register DCSR (at address 6C0Fh) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
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== Vectored Interrupt interrupt ==
The ASIC always provides an interrupt vector on interrupt request.
Bits2..1 of the IVR register are unused.
Bit0 of the IVR register controls whether DMA channel interrupts are automatically cleared. Raster interrupts are always automatically cleared regardless of this setting.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
==== Interrupt Vector vector used on Z80 IM2 mode ====
{| class="wikitable"
|-
!Interrupt Vectorvector
!Signal source
!Value
|A7..A3||ASIC||IVR register bits7..3
|-
|A2..A1||ASIC||00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA rasterRaster
|-
|A0||ASIC||Always 0
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== Known Flawsflaws==
The Amstrad Plus ASIC improved a lot of the old CPC's capability.
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==Internal Linkslinks==
*[[Arnold V specs]]
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==External Linkslinks==
*[http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC at Wikipedia] General information on ASICs.