Reset to Bus Control Delay Time trb 100 - ns
|'''A9, A8, DA7--DA0 (Address Mode) '''||Fig 9 |-|Address Setup Time tas 300 - ns |-|Address Hold Time tah 50 - ns |-|DA7--DA0 (Write Mode)'''||Fig. 10 |-|Write Data Pulse Width||tdw||1800||-||ns |-|Write Data Setup Time||tds||50||-||ns |-|Write Data Hold Time||tdh||100||-||ns |-|'''DA7--DA0 (Read Mode)'''||Fig. 11 |-|Read Data Access Time||tda||-||350||ns |-|'''DA7--DA0 (Inactive Mode)''' |-|Tristate Delay Time||tts||-||400||ns|}
Address Setup Time tas 300 - ns
Address Hold Time tah 50 - ns '''Fig 7. CLOCK AND BUS SIGNAL TIMING'''
DA7--DA0 (Write Mode) '''Fig8. 10 RESET TIMING'''
Write Data Pulse Width tdw 1800 - ns '''Fig 9. LATCH ADDRESS TIMING'''
Write Data Setup Time tds 50 - ns '''Fig 10. WRITE DATA TIMING'''
Write Data Hold Time tdh 100 - ns DA7--DA0 (Read Mode) Fig. 11 Read Data Access Time tda - 350 ns DA7--DA0 (Inactive Mode) Tristate Delay Time tts - 400 ns Fig 7. CLOCK AND BUS SIGNAL TIMING Fig 8. RESET TIMING Fig 9. LATCH ADDRESS TIMING Fig 10. WRITE DATA TIMING '''Fig 11. READ DATA TIMING'''
[[Category:Hardware]] [[Category:Datasheet]]
