Changes
Z80
,/* CPC Timings */
* Instructions IN r,(C) and OUT (C),r take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access. On Zilog manual, it is precised that one wait-state TW is automatically inserted after T2 on I/O access.
The CPC timings of some instructions will be altered if an interrupt happens. The interrupt test occurs on the last T-State state of the instruction, and if it's low, the Z80 will insert 2 wait states to acknowledge the interrupt.
So, instructions which end in the third or fourth T-State state relative to the read alignment for the next instruction fetch will be delayed by an extra 4 T-Statesstates. The few instructions which end in the first or second T-State state won't since the first instruction fetch/read in the interrupt won't be delayed an extra 4 T-Statesstates. [https://www.cpcwiki.eu/forum/programming/interrupt-wait/ Source]
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