Changes
Undo revision 118488 by [[Special:Contributions/Phi2x|Phi2x]] ([[User talk:Phi2x|talk]])
Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access
* The video hardware is given priority so that the display is not disrupted
