When the CPU accepts a maskable interrupt, both IFF1 and IFF2 are automatically reset, inhibiting further interrupts.
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| IFF2 || 1-bit || Store Stores the state of IFF1 during Non-Maskable Interrupts (NMI) || When an NMI occurs, the processor clears IFF1 to disable interrupts temporarily.
IFF2 stores the previous state of IFF1 so that after the NMI is handled, IFF1 can be restored to its original state.
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