Changes
/* Coordinates */
For a vram size of 512KB this gives image space heights of &1000,&800,&400,&200,&100 and &80.
* Confirmed with PSET and BMLX. When calculating the logical vram address of each line:
1) P1 mode is always 256 pixels wide, 4bpp (width (XIMM) and bpp (CLRM) settings with R6 are ignored). Therefore logical vram address of Y is defined as: (256/2)*y.
2) P2 mode is always 512 pixels wide, 4bpp (width (XIMM) and bpp (CLRM) settings with R6 are ignored). Therefore logical vram address of Y is defined as: (512/2)*y
3) In bitmap mode width (XIMM) and bpp (CLRM) settings are used. HSCN and C25M are ignored. Therefore logical vram address of Y is defined as: XIMM/4 when 2bpp, XIMM/2 when 4bpp, XIMM when 8bpp and XIMM*2 when 16bpp.
4) For the command-engine, standby mode is identical in operation to the bitmap mode.
5) Although the logical vram address of each line is calculated this way, a lot of the operations act as if it is in bitmap mode and when plotting pixels take into account the bpp setting from CLRM.
=== Registers ===
