* ''This is adapted from an article about the "Cathode Ray Tube Controller" by CPC scene member [[ChaRleyTroniC]]''
The '''CRTC''' (Cathode Ray Tube Controller) helps to generate the video signal of the Amstrad CPC.
CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.
However, this signal is present on provided to the expansion port. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions.
== DISPTMG ==
|2||Horizontal Sync Position ||00000000||46||When to start the HSync signal.
|-
|3||Horizontal and Vertical Sync Widths||VVVVHHHH||128+14||HSync pulse width in characters (0 means 16 only on some CRTCs. Needs to be at least 2 for Gate Array to change the video mode); VSync width in scan-lines (0 always means 16. Not present on all CRTCs, fixed to 16 lines on these).
|-
|4||Vertical Total (-1)||x0000000||38||Height of the screen, in characters.
|7||Vertical Sync Position||x0000000||30||When to start the VSync signal, in characters.
|-
|8||Interlace and Skew||xxxxxx00CCDDxxII||0||00CC: No interlace; 01Cursor Skew (Only in CRTCs 0, 3 and 4). DD: Interlace Sync Raster Scan Mode; 10Display Skew (Only in CRTCs 0, 3 and 4). II: No Interlace; 11: Interlace Sync and Video Raster Scan Mode.
|-
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||xxx00000||7||Maximum scan line address on CPC can hold between 0 and 7, higher values' upper bits are ignored
|-
|10||Cursor Start Raster||xBP00000||0||Cursor signal is not used on CPCconnected to the Gate Array but is provided to the expansion port. B = Blink On/Off; P = Blink Period Control (Slow/Fast). Sets first raster row of character that cursor is on to invert.
|-
|11||Cursor End Raster||xxx00000||0||Sets last raster row of character that cursor is on to invert
|-
|12||Display Start Address (High)||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address)
|-
|13||Display Start Address (Low)||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|15||Cursor Address (Low)||00000000||0
|-
|16||Light Pen Address (High)||xx000000||||Read Only. On CRTC1, bit6 of Status register goes to 0 when R16 is read
|-
|17||Light Pen Address (Low)||00000000||||Read Only. On CRTC1, bit6 of Status register goes to 0 when R17 is read
|-
|}
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|1||0||Read Status Register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only Only
|}
|1||0||-||-
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|1||0||Read from selected internal 6845 register||Read Only
|-
|1||1||Read from selected internal 6845 register||Read only Only
|-
|}
|9||Maximum Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write Only
|-
|10||Cursor Start Raster||Write Only||Write Only||Read Only/Write
|-
|11||Cursor End Raster||Write Only||Write Only||Read Only/Write
|-
|12||Display Start Address (High)||Read/Write||Write Only||Read/Write
'''Notes'''
* On type 0 The CRTC is not connected to the CPU's RD and 1WR pins, so the CRTC is not aware of the CPU bus I/O direction. Therefore, if a Write Only register is read frominstruction is used on a write register of the CRTC, "0" then a data is returnedsent to the CRTC.
* CRTC type 4 On types 0 and 1, if a Write Only register is the same as read from, "0" is returned. * CRTC type types 3. The registers also repeat as they do on and 4 are identical in every way, except for the type 3unlocking mechanism specific to the ASIC.
* See the document "Extra CPC Plus Hardware Information" for more details.
=== Horizontal and Vertical Sync (R3) ===
UM6845Type 0:*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
UM6845RType 1:*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
MC6845Type 2:*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
Pre-ASICTypes 3/ASIC4:*Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
=== Interlace and Skew (R8) ===
UM6845Types 0/3/4:*Bits 7..6 define the skew (delay ) of the CUDISP signal(00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 5..4 define the skew (delay ) of the DISPTMG signal(00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 3..2 are ignored.*Bits 1..0 define the interlace mode(00 = No Interlace; 01 = Interlace Sync; 10 = No Interlace; 11 = Interlace Sync and Video).
UM6845RTypes 1/2:*Bits 7..2 are ignored.*Bits 1..0 define the interlace mode.
MC6845:
Bits 7..2 are ignored.
Bits 1..0 define the interlace mode.
Pre-ASIC/ASICInterlace modes:Bits 7..6 are ignored.Bits 5..4 define the delay of the DISPTMG signal.Bits 3..2 are ignored.Bits 1..0 define the interlace mode.
[[File:CRTC Interlace modes.png]]
=== ASIC/Pre-ASIC and R10/R11 ===
The cursor raster registers R10/R11 act as status registers when read on Types 3 & 4. They behave as normal cursor raster registers upon write.
{| class="wikitable sortable"
|''Used for interlace and CRTC cursor blinking''
|}
No matter its type, the CRTC never buffers its counters.
The only value that is saved in a buffer in the CRTC is the video pointer because it is reloaded at each line start.
<br>
* [http://www.cpcwiki.eu/imgs/9/99/Elmar_Krieger-SPECIAL_EFFECTS.dsk some BASIC tools to detect CRTC types 0-1-2 and show some effects] by [[Elmar Krieger]] (DSK for Emulators)
* [[File:Shaker25Shaker26.dsk]] Shaker v2.5 - Suite of CRTC tests associated with the CPC CRTC compendium (many of them will not work correctly on emulators and that was the purpose of the tests, to help create more compatible emulation)
* [[File:Shaker addon.dsk]] Shaker Add-On (Pixel 1 Hard Scroll / Vertical Rupture all Crtc)