The 8KB extra memory, was a 4164 DRAM chip (64Kx1bit). The DRAMs 1bit databus didn't suit too well to the Z80s 8bit bus, moreover, the daughterboard didn't receive /RAS and /CAS signals which are usually required for DRAM addressing & DRAM refresh. So, even if it would have been functional, the RAM could have been only accessed via complicated software mechanisms; like loading the address LSBs into IR register, and then INning from address MSBs.
The two logic chips for address decoding (not connected, and non-functional, too) are more or less hidden under the robbon cable. Looking under it reveals a 74LS08 (Quad 2-Input NAND), and a 74LS32 (Quad 2-Input OR), as seen on Miguel Angel's photos. However, on Kevin Thacker's webpage, the second chip is listed as 74LS136 (Open-collector Quad 2-Input XOR) - so, it seems the daughterboards were randomly fitted with whatever cheaply available chips (possibly including damaged chips - ''can somebody verify that?'').
== More Pictures ==