[[Image:CPC 472 es.jpg|thumb|right|200px|Spanish Amstrad CPC 472]] The CPC 472 was a spanish version of the CPC [[464|464]] with additional (nonfunctional) 8 KB RAM. == Description ==
The reason [[Amstrad|Amstrad]] released a special version for the spanish market was a law ([[RD 1250/1985|RD 1250/1985]]) that said that every computer with up to 64kb should adhere to some rules - namely, have extra keys for the spanish language, and the video hardware had to be able to display spanish characters; otherwise an extra tax would be levied.
Later on Amstrad released a 472 with a proper spanish keyboard and the 8 extra kB as well. [[Image:Amstrad 472 motherboard.jpg|thumb|right|200px|Left side of the CPC472 motherboard, revealing the location for the presumely 8KB expansion memory.]]
The 8KB extra memory, was a 4164 DRAM chip (64Kx1bit). The DRAMs 1bit databus didn't suit too well to the Z80s 8bit bus, moreover, the daughterboard didn't receive /RAS and /CAS signals which are usually required for DRAM addressing & DRAM refresh. So, even if it would have been functional, the RAM could have been only accessed via complicated software mechanisms; like loading the address LSBs into IR register, and then INning from address MSBs. Because there was no space for a new chip, Amstrad designers took off one of the ROM chips, and put it in a daughter board, along with the 4164 chip. Wires connected pins at the ROM from the daughter board to the corresponding pins on the main board. The wires were hard enough to make difficult to turn the daughter board over and reveal the trick: no wires were connected from the DRAM chip to the main board. Even the supply pins were not connected!!
While based on the CPC 464, at least some of the 472s got the ROM v2 with [[Locomotive BASIC]] 1.1, which normally was built into the CPC [[664]].
File:Miguel Angel CPC472 Daughter PCB Bottom.jpg|Bottom, desoldered
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The 8KB extra memory, was a 4164 DRAM chip (64Kx1bit). The DRAMs 1bit databus didn't suit too well to the Z80s 8bit bus, moreover, the daughterboard didn't receive /RAS and /CAS signals which are usually required for DRAM addressing & DRAM refresh. So, even if it would have been functional, the RAM could have been only accessed via complicated software mechanisms; like loading the address LSBs into IR register, and then INning from address MSBs.
== More Pictures ==